[PATCH] D63476: [ARM] DLS/LE low-overhead loop code generation

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


================
Comment at: lib/Target/ARM/ARMFinalizeLoops.cpp:139
+          Revert = true;
+      }
+    }
----------------
if `Revert` is true here at some point, can we stop iterating over the rest of the blocks/instructions?


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Comment at: lib/Target/ARM/ARMISelDAGToDAG.cpp:2995
+
+        if (ID == Intrinsic::loop_decrement_reg) {
+          SDValue Elements = Int.getOperand(2);
----------------
nit: can this be simplified using `getIntrinsicID()`?


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Comment at: lib/Target/ARM/ARMISelDAGToDAG.cpp:3004
+            CurDAG->getMachineNode(ARM::t2LoopDec, dl,
+                               CurDAG->getVTList(MVT::i32, MVT::Other),
+                               Args);
----------------
another nit: indentation a bit off?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63476/new/

https://reviews.llvm.org/D63476