[PATCH] D63476: [ARM] DLS/LE low-overhead loop code generation

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: dmgreen, SjoerdMeijer, efriedma, t.p.northover.
Herald added subscribers: kristof.beyls, javed.absar, mgorny, qcolombet.
Herald added a project: LLVM.

Introduce three pseudo instructions to be used during DAG ISel to represent v8.1-m low-overhead loops. One maps to set_loop_iterations while loop_decrement_reg is lowered to two, so that we can separate the decrement and branching operations. The pseudo instructions are expanded pre-emission where we can still decide whether we actually want to generate a low-overhead loop. The pass currently bails, revering to an sub, icmp and br, in the cases where a call or stack spill/restore happens between the decrement and branching instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D63476

Files:
  lib/Target/ARM/ARM.h
  lib/Target/ARM/ARMFinalizeLoops.cpp
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMInstrThumb2.td
  lib/Target/ARM/ARMTargetMachine.cpp
  lib/Target/ARM/CMakeLists.txt
  test/CodeGen/ARM/O3-pipeline.ll
  test/Transforms/HardwareLoops/ARM/calls.ll
  test/Transforms/HardwareLoops/ARM/cond-mov.mir
  test/Transforms/HardwareLoops/ARM/massive.mir
  test/Transforms/HardwareLoops/ARM/revert-after-call.mir
  test/Transforms/HardwareLoops/ARM/revert-after-spill.mir
  test/Transforms/HardwareLoops/ARM/simple-do.ll
  test/Transforms/HardwareLoops/ARM/structure.ll
  test/Transforms/HardwareLoops/ARM/switch.mir

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