[PATCH] D62890: [PowerPC] Merge consecutive stores of vector elements before types are legalized

[Nirav Dave via Phabricator via llvm-commits]

niravd added a comment.

By double check, I just meant to look at the results again with isTypeLegal checked, which is where we are?

FWIW, It's probably fine to do something like isTypeLegal with allowsMemoryAccess, though there will likely be more changes in other backends,. I expect most to be mundane. It may be worth it to update and see if others are motivated to look into real regressions.

In D62890#1549589 <https://reviews.llvm.org/D62890#1549589>, @lkail wrote:

> @niravd Thanks for pointing out my mistake. I tried swapping out `TIL.isTypeLegal` with `isTypeLegal`, code generated for PowerPC is not what I expect, cuz `TIL.allowsMemoryAccess` will return false if `Ty` is something like `v3i32`. Also this change will break some regression tests of `SystemZ` and `X86`. And I don't quite understand the meaning of 'double check' here, could you please explain more?





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  https://reviews.llvm.org/D62890/new/

https://reviews.llvm.org/D62890