[PATCH] D62890: [PowerPC] Merge consecutive stores of vector elements before types are legalized

[Kai Luo via Phabricator via llvm-commits]

lkail added a comment.

@niravd Thanks for pointing out my mistake. I tried swapping out `TIL.isTypeLegal` with `isTypeLegal`, code generated for PowerPC is not what I expect, cuz `TIL.allowsMemoryAccess` will return false if `Ty` is something like `v3i32`. Also this change will break some regression tests of `SystemZ` and `X86`. And I don't quite understand the meaning of 'double check' here, could you please explain more?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62890/new/

https://reviews.llvm.org/D62890