[PATCH] D59990: AMDGPU. Divergence driven ISel. Assign register class for cross block values according to the divergence.

[Alexander via Phabricator via llvm-commits]

alex-t added a comment.

In D59990#1530704 <https://reviews.llvm.org/D59990#1530704>, @hakzsam wrote:

> In D59990#1530603 <https://reviews.llvm.org/D59990#1530603>, @alex-t wrote:
>
> > In D59990#1530511 <https://reviews.llvm.org/D59990#1530511>, @hakzsam wrote:
> >
> > > > I have updated the change ttps://reviews.llvm.org/D62614 this Sunday.
> > > >  The new one takes completely different approach. I'd appreciate very much If you could try  it.
> > >
> > > D62614 <https://reviews.llvm.org/D62614> doesn't fix the issue.
> >
> >
> > Okay. I'm about to start partial revert of the change. 
> >  Could you please provide me test cases so that I can check if my further fixes help.
>
>
> See below the good and bad outputs for one CTS failure:
>
> GOOD: https://hastebin.com/muwuwivofu
>  BAD: https://hastebin.com/gofawejoku
>
> Thanks again for looking into this.
>
> Note that this change also breaks https://bugs.freedesktop.org/show_bug.cgi?id=110811


I investigated the failed case. The reason is again in use of the value that is uniform inside the loop but the loop has divergent exit.
We rely on LCSSA PHIs to handle this. Unfortunately, Early CSE pass mistakenly removes them.
I have one line fix and the review for it: https://reviews.llvm.org/D63489
Could you possibly check if it helps in this particular case? If yes it maybe worth checking others...


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