[PATCH] D63407: AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyext

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, rampitec, nhaehnle.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, kristof.beyls, rovka, yaxunl, wdng, jvesely, kzhuravl.

This needs different handling if the source is known to be a valid
condition or not. Handle turning it into shifts or a select during
regbankselect.


https://reviews.llvm.org/D63407

Files:
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir

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