[PATCH] D63202: [AMDGPU] gfx1010 premlane instructions

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 12 08:16:15 PDT 2019


rampitec marked 2 inline comments as done.
rampitec added inline comments.


================
Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:1441
+// llvm.amdgcn.permlane16 <old> <src0> <src1> <src2> <fi> <bound_control>
+def int_amdgcn_permlane16 :
+  Intrinsic<[llvm_i32_ty],
----------------
arsenm wrote:
> Do these need to be marked as SourceOfDivergence?
Probably, but in a separate patch. It has vgpr arguments, so shall be treated as divergent anyway I think.


================
Comment at: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:3007
 
+bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
+  const unsigned Opc = Inst.getOpcode();
----------------
arsenm wrote:
> Missing assembler test
It is not missing. There is a huge stack of dependent changes, so tests will follow. They can hardly be separated.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63202/new/

https://reviews.llvm.org/D63202





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