[PATCH] D63202: [AMDGPU] gfx1010 premlane instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:1441
+// llvm.amdgcn.permlane16 <old> <src0> <src1> <src2> <fi> <bound_control>
+def int_amdgcn_permlane16 :
+  Intrinsic<[llvm_i32_ty],
----------------
Do these need to be marked as SourceOfDivergence?


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Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:1443
+  Intrinsic<[llvm_i32_ty],
+            [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
+            [IntrNoMem, IntrConvergent]>;
----------------
A bunch of these should be immarg


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Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:1449
+  Intrinsic<[llvm_i32_ty],
+            [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
+            [IntrNoMem, IntrConvergent]>;
----------------
Ditto


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Comment at: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:3007
 
+bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
+  const unsigned Opc = Inst.getOpcode();
----------------
Missing assembler test


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  https://reviews.llvm.org/D63202/new/

https://reviews.llvm.org/D63202