[llvm] r362854 - LoopDistribute: Add testcase where SCEV wants to insert a runtime
Michael Kruse via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 11 20:56:20 PDT 2019
Could you please add a "Differential Revision:
https://reviews.llvm.org/D63008" line when committing? This allows
directly going to the review when browsing the svn/git history.
Michael
Am Fr., 7. Juni 2019 um 18:14 Uhr schrieb Matt Arsenault via
llvm-commits <llvm-commits at lists.llvm.org>:
>
> Author: arsenm
> Date: Fri Jun 7 16:17:38 2019
> New Revision: 362854
>
> URL: http://llvm.org/viewvc/llvm-project?rev=362854&view=rev
> Log:
> LoopDistribute: Add testcase where SCEV wants to insert a runtime
> check.
>
> Only the memory based checks were being tested. Prepare for fix in
> convergent handling.
>
> Added:
> llvm/trunk/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll
>
> Added: llvm/trunk/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll?rev=362854&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll (added)
> +++ llvm/trunk/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll Fri Jun 7 16:17:38 2019
> @@ -0,0 +1,145 @@
> +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
> +; RUN: opt -basicaa -loop-distribute -enable-loop-distribute -S -enable-mem-access-versioning=0 < %s | FileCheck %s
> +
> +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
> +
> +; PredicatedScalarEvolution decides it needs to insert a bounds check
> +; not based on memory access.
> +
> +define void @f(i32* noalias %a, i32* noalias %b, i32* noalias %c, i32* noalias %d, i32* noalias %e, i64 %N) {
> +
> +; CHECK-LABEL: @f(
> +; CHECK-NEXT: entry:
> +; CHECK-NEXT: [[A2:%.*]] = ptrtoint i32* [[A:%.*]] to i64
> +; CHECK-NEXT: br label [[FOR_BODY_LVER_CHECK:%.*]]
> +; CHECK: for.body.lver.check:
> +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], -1
> +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
> +; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
> +; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
> +; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
> +; CHECK-NEXT: [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
> +; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
> +; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0
> +; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0
> +; CHECK-NEXT: [[TMP6:%.*]] = select i1 false, i1 [[TMP4]], i1 [[TMP5]]
> +; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
> +; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
> +; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
> +; CHECK-NEXT: [[TMP10:%.*]] = or i1 false, [[TMP9]]
> +; CHECK-NEXT: [[MUL3:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])
> +; CHECK-NEXT: [[MUL_RESULT4:%.*]] = extractvalue { i64, i1 } [[MUL3]], 0
> +; CHECK-NEXT: [[MUL_OVERFLOW5:%.*]] = extractvalue { i64, i1 } [[MUL3]], 1
> +; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[A2]], [[MUL_RESULT4]]
> +; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[A2]], [[MUL_RESULT4]]
> +; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[TMP12]], [[A2]]
> +; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i64 [[TMP11]], [[A2]]
> +; CHECK-NEXT: [[TMP15:%.*]] = select i1 false, i1 [[TMP13]], i1 [[TMP14]]
> +; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[MUL_OVERFLOW5]]
> +; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP10]], [[TMP16]]
> +; CHECK-NEXT: br i1 [[TMP17]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]
> +; CHECK: for.body.ph.lver.orig:
> +; CHECK-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]
> +; CHECK: for.body.lver.orig:
> +; CHECK-NEXT: [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[ADD_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
> +; CHECK-NEXT: [[IND1_LVER_ORIG:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC1_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
> +; CHECK-NEXT: [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
> +; CHECK-NEXT: [[MUL_EXT_LVER_ORIG:%.*]] = zext i32 [[MUL_LVER_ORIG]] to i64
> +; CHECK-NEXT: [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
> +; CHECK-NEXT: [[LOADA_LVER_ORIG:%.*]] = load i32, i32* [[ARRAYIDXA_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[MUL_EXT_LVER_ORIG]]
> +; CHECK-NEXT: [[LOADB_LVER_ORIG:%.*]] = load i32, i32* [[ARRAYIDXB_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[MULA_LVER_ORIG:%.*]] = mul i32 [[LOADB_LVER_ORIG]], [[LOADA_LVER_ORIG]]
> +; CHECK-NEXT: [[ADD_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
> +; CHECK-NEXT: [[INC1_LVER_ORIG]] = add i32 [[IND1_LVER_ORIG]], 1
> +; CHECK-NEXT: [[ARRAYIDXA_PLUS_4_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[ADD_LVER_ORIG]]
> +; CHECK-NEXT: store i32 [[MULA_LVER_ORIG]], i32* [[ARRAYIDXA_PLUS_4_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[ARRAYIDXD_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[D:%.*]], i64 [[MUL_EXT_LVER_ORIG]]
> +; CHECK-NEXT: [[LOADD_LVER_ORIG:%.*]] = load i32, i32* [[ARRAYIDXD_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[ARRAYIDXE_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[E:%.*]], i64 [[MUL_EXT_LVER_ORIG]]
> +; CHECK-NEXT: [[LOADE_LVER_ORIG:%.*]] = load i32, i32* [[ARRAYIDXE_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[MULC_LVER_ORIG:%.*]] = mul i32 [[LOADD_LVER_ORIG]], [[LOADE_LVER_ORIG]]
> +; CHECK-NEXT: [[ARRAYIDXC_LVER_ORIG:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i64 [[MUL_EXT_LVER_ORIG]]
> +; CHECK-NEXT: store i32 [[MULC_LVER_ORIG]], i32* [[ARRAYIDXC_LVER_ORIG]], align 4
> +; CHECK-NEXT: [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[ADD_LVER_ORIG]], [[N]]
> +; CHECK-NEXT: br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END:%.*]], label [[FOR_BODY_LVER_ORIG]]
> +; CHECK: for.body.ph.ldist1:
> +; CHECK-NEXT: br label [[FOR_BODY_LDIST1:%.*]]
> +; CHECK: for.body.ldist1:
> +; CHECK-NEXT: [[IND_LDIST1:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LDIST1]] ], [ [[ADD_LDIST1:%.*]], [[FOR_BODY_LDIST1]] ]
> +; CHECK-NEXT: [[IND1_LDIST1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LDIST1]] ], [ [[INC1_LDIST1:%.*]], [[FOR_BODY_LDIST1]] ]
> +; CHECK-NEXT: [[MUL_LDIST1:%.*]] = mul i32 [[IND1_LDIST1]], 2
> +; CHECK-NEXT: [[MUL_EXT_LDIST1:%.*]] = zext i32 [[MUL_LDIST1]] to i64
> +; CHECK-NEXT: [[ARRAYIDXA_LDIST1:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[MUL_EXT_LDIST1]]
> +; CHECK-NEXT: [[LOADA_LDIST1:%.*]] = load i32, i32* [[ARRAYIDXA_LDIST1]], align 4
> +; CHECK-NEXT: [[ARRAYIDXB_LDIST1:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[MUL_EXT_LDIST1]]
> +; CHECK-NEXT: [[LOADB_LDIST1:%.*]] = load i32, i32* [[ARRAYIDXB_LDIST1]], align 4
> +; CHECK-NEXT: [[MULA_LDIST1:%.*]] = mul i32 [[LOADB_LDIST1]], [[LOADA_LDIST1]]
> +; CHECK-NEXT: [[ADD_LDIST1]] = add nuw nsw i64 [[IND_LDIST1]], 1
> +; CHECK-NEXT: [[INC1_LDIST1]] = add i32 [[IND1_LDIST1]], 1
> +; CHECK-NEXT: [[ARRAYIDXA_PLUS_4_LDIST1:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[ADD_LDIST1]]
> +; CHECK-NEXT: store i32 [[MULA_LDIST1]], i32* [[ARRAYIDXA_PLUS_4_LDIST1]], align 4
> +; CHECK-NEXT: [[EXITCOND_LDIST1:%.*]] = icmp eq i64 [[ADD_LDIST1]], [[N]]
> +; CHECK-NEXT: br i1 [[EXITCOND_LDIST1]], label [[FOR_BODY_PH:%.*]], label [[FOR_BODY_LDIST1]]
> +; CHECK: for.body.ph:
> +; CHECK-NEXT: br label [[FOR_BODY:%.*]]
> +; CHECK: for.body:
> +; CHECK-NEXT: [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
> +; CHECK-NEXT: [[IND1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH]] ], [ [[INC1:%.*]], [[FOR_BODY]] ]
> +; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[IND1]], 2
> +; CHECK-NEXT: [[MUL_EXT:%.*]] = zext i32 [[MUL]] to i64
> +; CHECK-NEXT: [[ADD]] = add nuw nsw i64 [[IND]], 1
> +; CHECK-NEXT: [[INC1]] = add i32 [[IND1]], 1
> +; CHECK-NEXT: [[ARRAYIDXD:%.*]] = getelementptr inbounds i32, i32* [[D]], i64 [[MUL_EXT]]
> +; CHECK-NEXT: [[LOADD:%.*]] = load i32, i32* [[ARRAYIDXD]], align 4
> +; CHECK-NEXT: [[ARRAYIDXE:%.*]] = getelementptr inbounds i32, i32* [[E]], i64 [[MUL_EXT]]
> +; CHECK-NEXT: [[LOADE:%.*]] = load i32, i32* [[ARRAYIDXE]], align 4
> +; CHECK-NEXT: [[MULC:%.*]] = mul i32 [[LOADD]], [[LOADE]]
> +; CHECK-NEXT: [[ARRAYIDXC:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 [[MUL_EXT]]
> +; CHECK-NEXT: store i32 [[MULC]], i32* [[ARRAYIDXC]], align 4
> +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[ADD]], [[N]]
> +; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]]
> +; CHECK: for.end:
> +; CHECK-NEXT: ret void
> +entry:
> + br label %for.body
> +
> +for.body: ; preds = %for.body, %entry
> + %ind = phi i64 [ 0, %entry ], [ %add, %for.body ]
> + %ind1 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
> +
> + %mul = mul i32 %ind1, 2
> + %mul_ext = zext i32 %mul to i64
> +
> +
> + %arrayidxA = getelementptr inbounds i32, i32* %a, i64 %mul_ext
> + %loadA = load i32, i32* %arrayidxA, align 4
> +
> + %arrayidxB = getelementptr inbounds i32, i32* %b, i64 %mul_ext
> + %loadB = load i32, i32* %arrayidxB, align 4
> +
> + %mulA = mul i32 %loadB, %loadA
> +
> + %add = add nuw nsw i64 %ind, 1
> + %inc1 = add i32 %ind1, 1
> +
> + %arrayidxA_plus_4 = getelementptr inbounds i32, i32* %a, i64 %add
> + store i32 %mulA, i32* %arrayidxA_plus_4, align 4
> +
> + %arrayidxD = getelementptr inbounds i32, i32* %d, i64 %mul_ext
> + %loadD = load i32, i32* %arrayidxD, align 4
> +
> + %arrayidxE = getelementptr inbounds i32, i32* %e, i64 %mul_ext
> + %loadE = load i32, i32* %arrayidxE, align 4
> +
> + %mulC = mul i32 %loadD, %loadE
> +
> + %arrayidxC = getelementptr inbounds i32, i32* %c, i64 %mul_ext
> + store i32 %mulC, i32* %arrayidxC, align 4
> +
> + %exitcond = icmp eq i64 %add, %N
> + br i1 %exitcond, label %for.end, label %for.body
> +
> +for.end: ; preds = %for.body
> + ret void
> +}
>
>
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