[PATCH] D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V

[Alex Bradbury via Phabricator via llvm-commits]

asb requested changes to this revision.
asb added a comment.
This revision now requires changes to proceed.
Herald added subscribers: Jim, benna, psnobl.

Hi Lewis - might you get a chance to update this with the changes suggested by @jrtc27? I made another minor comment too.



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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:1868
+      // Validate & create a 12-bit signed immediate operand.
+      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+        uint64_t CVal = C->getSExtValue();
----------------
You can use auto in this and the other cases: https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable


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  rL LLVM

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  https://reviews.llvm.org/D54093/new/

https://reviews.llvm.org/D54093