[llvm] r362516 - [Tests] Autogen tests so that diffs for a future change are understandable
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 4 09:15:19 PDT 2019
Author: reames
Date: Tue Jun 4 09:15:19 2019
New Revision: 362516
URL: http://llvm.org/viewvc/llvm-project?rev=362516&view=rev
Log:
[Tests] Autogen tests so that diffs for a future change are understandable
Modified:
llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll
llvm/trunk/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
Modified: llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll?rev=362516&r1=362515&r2=362516&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Tue Jun 4 09:15:19 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -indvars -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
@@ -5,11 +6,28 @@ target datalayout = "e-p:64:64:64-i1:8:8
; IV with constant start, preinc and postinc sign extends, with and without NSW.
; IV rewrite only removes one sext. WidenIVs removes all three.
define void @postincConstIV(i8* %base, i32 %limit) nounwind {
+; CHECK-LABEL: @postincConstIV(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMIT:%.*]] to i64
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i8 0, i8* [[PREADR]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i8 0, i8* [[POSTADR]]
+; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr inbounds i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]]
+; CHECK-NEXT: [[COND:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: br label [[RETURN:%.*]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
entry:
br label %loop
-; CHECK: loop:
-; CHECK-NOT: sext
-; CHECK: exit:
loop:
%iv = phi i32 [ %postiv, %loop ], [ 0, %entry ]
%ivnsw = phi i32 [ %postivnsw, %loop ], [ 0, %entry ]
@@ -36,14 +54,33 @@ return:
; with and without NSW.
; As with postincConstIV, WidenIVs removes all three sexts.
define void @postincVarIV(i8* %base, i32 %init, i32 %limit) nounwind {
+; CHECK-LABEL: @postincVarIV(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[PRECOND:%.*]] = icmp sgt i32 [[LIMIT:%.*]], [[INIT:%.*]]
+; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[RETURN:%.*]]
+; CHECK: loop.preheader:
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INIT]] to i64
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i8 0, i8* [[PREADR]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i8 0, i8* [[POSTADR]]
+; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMIT]] to i64
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: br label [[RETURN]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
entry:
%precond = icmp sgt i32 %limit, %init
br i1 %precond, label %loop, label %return
-; CHECK: loop:
-; CHECK-NOT: sext
-; CHECK: wide.trip.count = sext
-; CHECK-NOT: sext
-; CHECK: exit:
loop:
%iv = phi i32 [ %postiv, %loop ], [ %init, %entry ]
%ivnsw = phi i32 [ %postivnsw, %loop ], [ %init, %entry ]
@@ -72,18 +109,57 @@ return:
; %inneriv can be widened only after proving it has no signed-overflow
; based on the loop test.
define void @nestedIV(i8* %address, i32 %limit) nounwind {
+; CHECK-LABEL: @nestedIV(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[LIMITDEC:%.*]] = add i32 [[LIMIT:%.*]], -1
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMIT]] to i64
+; CHECK-NEXT: br label [[OUTERLOOP:%.*]]
+; CHECK: outerloop:
+; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, i8* [[ADDRESS:%.*]], i64 [[TMP1]]
+; CHECK-NEXT: store i8 0, i8* [[ADR1]]
+; CHECK-NEXT: br label [[INNERPREHEADER:%.*]]
+; CHECK: innerpreheader:
+; CHECK-NEXT: [[INNERPRECMP:%.*]] = icmp sgt i32 [[LIMITDEC]], [[INNERCOUNT]]
+; CHECK-NEXT: br i1 [[INNERPRECMP]], label [[INNERLOOP_PREHEADER:%.*]], label [[OUTERMERGE]]
+; CHECK: innerloop.preheader:
+; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[INNERCOUNT]] to i64
+; CHECK-NEXT: br label [[INNERLOOP:%.*]]
+; CHECK: innerloop:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP2]], [[INNERLOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNERLOOP]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[ADR2:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i8 0, i8* [[ADR2]]
+; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i8 0, i8* [[ADR3]]
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMITDEC]] to i64
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
+; CHECK: innerexit:
+; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32
+; CHECK-NEXT: br label [[OUTERMERGE]]
+; CHECK: outermerge:
+; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP3]], [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ]
+; CHECK-NEXT: [[ADR4:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV1]]
+; CHECK-NEXT: store i8 0, i8* [[ADR4]]
+; CHECK-NEXT: [[OFS5:%.*]] = sext i32 [[INNERCOUNT_MERGE]] to i64
+; CHECK-NEXT: [[ADR5:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[OFS5]]
+; CHECK-NEXT: store i8 0, i8* [[ADR5]]
+; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
+; CHECK-NEXT: [[TMP47:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT2]], [[TMP0]]
+; CHECK-NEXT: br i1 [[TMP47]], label [[OUTERLOOP]], label [[RETURN:%.*]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
entry:
%limitdec = add i32 %limit, -1
br label %outerloop
-; CHECK: outerloop:
-;
; Eliminate %ofs1 after widening outercount.
-; CHECK-NOT: sext
-; CHECK: getelementptr
-;
; IV rewriting hoists a gep into this block. We don't like that.
-; CHECK-NOT: getelementptr
outerloop:
%outercount = phi i32 [ %outerpostcount, %outermerge ], [ 0, %entry ]
%innercount = phi i32 [ %innercount.merge, %outermerge ], [ 0, %entry ]
@@ -99,13 +175,8 @@ innerpreheader:
%innerprecmp = icmp sgt i32 %limitdec, %innercount
br i1 %innerprecmp, label %innerloop, label %outermerge
-; CHECK: innerloop:
-;
; Eliminate %ofs2 after widening inneriv.
; Eliminate %ofs3 after normalizing sext(innerpostiv)
-; CHECK-NOT: sext
-; CHECK: getelementptr
-;
; FIXME: We should check that indvars does not increase the number of
; IVs in this loop. sext elimination plus LFTR currently results in 2 final
; IVs. Waiting to remove LFTR.
@@ -128,12 +199,7 @@ innerexit:
%innercount.lcssa = phi i32 [ %innerpostiv, %innerloop ]
br label %outermerge
-; CHECK: outermerge:
-;
; Eliminate %ofs4 after widening outercount
-; CHECK-NOT: sext
-; CHECK: getelementptr
-;
; TODO: Eliminate %ofs5 after removing lcssa
outermerge:
%innercount.merge = phi i32 [ %innercount.lcssa, %innerexit ], [ %innercount, %innerpreheader ]
Modified: llvm/trunk/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll?rev=362516&r1=362515&r2=362516&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll Tue Jun 4 09:15:19 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -indvars < %s | FileCheck %s
; Provide legal integer types.
@@ -5,6 +6,34 @@ target datalayout = "n8:16:32:64"
define void @test1(float* nocapture %autoc, float* nocapture %data, float %d, i32 %data_len, i32 %sample) nounwind {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[DATA_LEN:%.*]], [[SAMPLE:%.*]]
+; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i32 [[DATA_LEN]], [[SAMPLE]]
+; CHECK-NEXT: br i1 [[CMP4]], label [[FOR_END:%.*]], label [[FOR_BODY_PREHEADER:%.*]]
+; CHECK: for.body.preheader:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDVARS_IV]] to i32
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[SAMPLE]]
+; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD]] to i64
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[DATA:%.*]], i64 [[IDXPROM]]
+; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP1]], [[D:%.*]]
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[AUTOC:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[ADD3:%.*]] = fadd float [[TMP2]], [[MUL]]
+; CHECK-NEXT: store float [[ADD3]], float* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SUB]] to i64
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]]
+; CHECK: for.end.loopexit:
+; CHECK-NEXT: br label [[FOR_END]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%sub = sub i32 %data_len, %sample
%cmp4 = icmp eq i32 %data_len, %sample
@@ -30,12 +59,7 @@ for.body:
for.end: ; preds = %for.body, %entry
ret void
-; CHECK-LABEL: @test1(
; check that we turn the IV test into an eq.
-; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK: %wide.trip.count = zext i32 %sub to i64
-; CHECK: %exitcond = icmp ne i64 %indvars.iv.next, %wide.trip.count
-; CHECK: br i1 %exitcond, label %for.body, label %for.end.loopexit
}
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