[PATCH] D62604: [CodeGen] Generic Hardware Loop Support

[Markus Lavin via Phabricator via llvm-commits]

markus added a comment.

In D62604#1528977 <https://reviews.llvm.org/D62604#1528977>, @samparker wrote:

> I would expect many targets to have some kind of validity check late on in the pipeline. loop.decrement.reg is designed so that it could just be selected to a machine sub, as the IV chain still exists along with the icmp and br. I have assumed that because the intrinsic behaves like a sub, any target should be able to, hopefully trivially, fall back to a machine sub late on. Is this something that would be difficult for you..? The loop.decrement, which produces an i1, would cause more problems but this framework allows the backend to make the best decision for itself.


Makes sense. Always setting `CounterInReg` and iselecting the resulting `loop.decrement.reg` as a `sub` (possibly with some additional annotation so that it can easily be removed later) would probably work well. Perhaps you could add something to the intrinsic documentation stating that it is designed to look and act as a `sub` for that particular purpose.


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