[PATCH] D62847: [PowerPC] reorder LSR and PPCCTRLoops pass

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: hfinkel, jsji, nemanjai, steven.zhang.
Herald added subscribers: asbirlea, hiraditya.
Herald added a project: LLVM.

Currently pass `LSR` runs before `PPCCTRLoops`, we meet some problem with this order because of the `icmp` inside loop which compares iteration indexed and loop trip count. In pass `LSR`, we always treat that `icmp` as a valid `ICmpZero` type `LSRUse`. But this is not true because in later pass `PPCCTRLoops`, we may replace this `icmp` with ctrloop instruction `bdnz`. So we may get suboptimal code based on this order.

Reordering `LSR` and `PPCCTRLoops` makes `LSR` know precisely whether the `icmp` replaced or kept in `PPCCTRLoops`

Get improvement for most benchmarks of SPEC CPU2017 on Power9. Biggest gain is xz, about 3.5%. No degradation found.


https://reviews.llvm.org/D62847

Files:
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/addi-licm.ll
  llvm/test/CodeGen/PowerPC/ctrloop-le.ll
  llvm/test/CodeGen/PowerPC/ctrloop-lt.ll
  llvm/test/CodeGen/PowerPC/ctrloop-ne.ll
  llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
  llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll
  llvm/test/CodeGen/PowerPC/stwu-sched.ll
  llvm/test/CodeGen/PowerPC/unal-altivec.ll
  llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

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