[PATCH] D62667: [ARM] Add the non-MVE instructions in Arm v8.1-M.

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

I will continue going over this tomorrow.



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Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:5128
+  bits<4> Rn;
+  let isBranch = 0;
+  let Inst{22-20} = 0b100;
----------------
I think isTerminator can also be = 0, I can't remember seeing anything about it needing to be at the end of a basic block.


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Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:2300
   let Inst{3-0}   = 0b0000;
+  let Predicates = [HasVFP2];
 }
----------------
Where has this come from..?


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Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:2672
+                oops, !con(iops, (ins t2addrmode_imm7s4:$addr)),
+                IndexModePost, "$addr", "" > {
+    let DecoderMethod = "DecodeVSTRVLDR_SYSREG_off";
----------------
Is this correct? What is IndexModePost?


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Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:2687
+                !con(oops, (outs GPRnopc:$wb)),
+                !con(iops, (ins t2_addr_offset_none:$Rn,
+                                t2am_imm7s4_offset:$addr)),
----------------
Why does the post form have one more operand than the pre? This doesn't really look like the existing pre/post load/store instructions.


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Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:264
+
+def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
+                                              LR, ZR)> {
----------------
I've just came here from the CSEL instructions, so forgive my limited scope, but why can't this register class access SP?


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Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:341
+// MVE Condition code register.
+def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
+//  let CopyCost = -1;  // Don't allow copying of status registers.
----------------
Is the i32 type just to copy us to easily copy the value around?


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Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:343
+//  let CopyCost = -1;  // Don't allow copying of status registers.
+  let AltOrders = [(add VPR)];
+}
----------------
Not needed.


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  https://reviews.llvm.org/D62667/new/

https://reviews.llvm.org/D62667