[PATCH] D62667: [ARM] Add the non-MVE instructions in Arm v8.1-M.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.

To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need some new
addressing modes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62667

Files:
  llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def
  llvm/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/test/CodeGen/ARM/ipra-reg-usage.ll
  llvm/test/MC/ARM/clrm-asm.s
  llvm/test/MC/ARM/thumbv8.1m-vmrs-vmsr.s
  llvm/test/MC/ARM/thumbv8.1m.s
  llvm/test/MC/ARM/vscclrm-asm.s
  llvm/test/MC/ARM/vstrldr_sys.s
  llvm/test/MC/Disassembler/ARM/clrm.txt
  llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt
  llvm/test/MC/Disassembler/ARM/thumbv8.1m-vmrs-vmsr.txt
  llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
  llvm/test/MC/Disassembler/ARM/vscclrm.txt
  llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt

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