[PATCH] D62599: [AArch64][SVE2] Asm: support SVE2 store instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


================
Comment at: test/MC/AArch64/SVE/stnt1b-diagnostics.s:26
 stnt1b z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: stnt1b z0.s, p0, [x0]
----------------
chill wrote:
> Is my understanding correct that we're interpreting an alias in a different way, but this happens only on error?
> 
The error has changed because a vector plus scalar form of `stnt1b` has been added and it's being matched differently.

`stnt1b z0.s, p0, [x0]` is now valid until the base `[x0]`, the following output from the asm-matcher might better explain it:

Before
```
echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher
        .text
AsmMatcher: found 6 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:8: error: invalid element width
stnt1b z0.s, p0, [x0]
       ^
```

After
```
echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher                                                                                                               
        .text
AsmMatcher: found 16 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:19: error: invalid operand for instruction
stnt1b z0.s, p0, [x0]
                  ^
```


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62599/new/

https://reviews.llvm.org/D62599