[PATCH] D62599: [AArch64][SVE2] Asm: support SVE2 store instructions

[Momchil Velikov via Phabricator via llvm-commits]

chill added inline comments.


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Comment at: test/MC/AArch64/SVE/stnt1b-diagnostics.s:26
 stnt1b z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: stnt1b z0.s, p0, [x0]
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Is my understanding correct that we're interpreting an alias in a different way, but this happens only on error?



Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62599/new/

https://reviews.llvm.org/D62599