[PATCH] D62415: [X86-64] Fix 256-bit SET0 lowering for non-VLX targets

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D62415#1521236 <https://reviews.llvm.org/D62415#1521236>, @craig.topper wrote:

> In D62415#1521084 <https://reviews.llvm.org/D62415#1521084>, @RKSimon wrote:
>
> > @greened This is causing EXPENSIVE_CHECKS buildbot failures - can you fix or shall I revert for now?
> >
> >   $ ":" "RUN: at line 4"
> >   $ "e:\llvm\ninja\bin\llc.exe" "-mtriple=x86_64--" "-mattr=+avx512f" "-o" "-" "E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir"
> >   # command stderr:
> >  
> >   # After Instruction Selection
> >   # Machine code for function main: IsSSA, NoPHIs, TracksLiveness, NoVRegs
> >  
> >   bb.0.bb0:
> >     renamable $ymm16 = AVX512_256_SET0
> >     VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
> >     RET 0
> >  
> >   bb.1.bb0:
> >     %0:vr256 = AVX512_256_SET0
> >     VMOVAPSYmr $rip, 1, $noreg, @tst_, $noreg, killed %0:vr256 :: (store 32 into %ir.lsr.iv1, align 64)
> >     RET 0
> >  
> >   # End machine code for function main.
> >  
> >   *** Bad machine code: Function has NoVRegs property but there are VReg operands ***
> >   - function:    main
> >   LLVM ERROR: Found 1 machine code errors.
> >   Stack dump:
> >   0.      Program arguments: e:\llvm\ninja\bin\llc.exe -mtriple=x86_64-- -mattr=+avx512f -o - E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir
> >   1.      Running pass 'Function Pass Manager' on module 'E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir'.
> >   2.      Running pass 'Verify generated machine code' on function '@main'
> >
>
>
> I'm working on a fix for this.


Should be fixed after r361991


Repository:
  rL LLVM

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  https://reviews.llvm.org/D62415/new/

https://reviews.llvm.org/D62415