[PATCH] D62492: [AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.
Michael Liao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 09:26:58 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL361847: [AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register. (authored by hliao, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D62492?vs=201556&id=201692#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62492/new/
https://reviews.llvm.org/D62492
Files:
llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/trunk/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
Index: llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -588,7 +588,9 @@
}
if (UseMI->isPHI()) {
- if (!TRI->isSGPRReg(MRI, Use.getReg()))
+ const TargetRegisterClass *UseRC = MRI.getRegClass(Use.getReg());
+ if (!TRI->isSGPRReg(MRI, Use.getReg()) &&
+ UseRC != &AMDGPU::VReg_1RegClass)
hasVGPRUses++;
continue;
}
@@ -633,8 +635,10 @@
if ((!TRI->isVGPR(MRI, PHIRes) && RC0 != &AMDGPU::VReg_1RegClass) &&
(hasVGPRInput || hasVGPRUses > 1)) {
+ LLVM_DEBUG(dbgs() << "Fixing PHI: " << MI);
TII->moveToVALU(MI);
} else {
+ LLVM_DEBUG(dbgs() << "Legalizing PHI: " << MI);
TII->legalizeOperands(MI, MDT);
}
Index: llvm/trunk/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
@@ -16,3 +16,47 @@
%6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc
%7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc
...
+
+# Test to ensure i1 phi copies from scalar registers through another phi won't
+# be promoted into vector ones.
+# GCN-LABEL: name: fix-sgpr-i1-phi-copies
+# GCN: .8:
+# GCN-NOT: vreg_64 = PHI
+---
+name: fix-sgpr-i1-phi-copies
+tracksRegLiveness: true
+body: |
+ bb.9:
+ S_BRANCH %bb.0
+
+ bb.4:
+ S_CBRANCH_SCC1 %bb.6, implicit undef $scc
+
+ bb.5:
+ %3:vreg_1 = IMPLICIT_DEF
+
+ bb.6:
+ %4:vreg_1 = PHI %2:sreg_64, %bb.4, %3:vreg_1, %bb.5
+
+ bb.7:
+ %5:vreg_1 = PHI %2:sreg_64, %bb.3, %4:vreg_1, %bb.6
+ S_BRANCH %bb.8
+
+ bb.0:
+ S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+
+ bb.1:
+ %0:sreg_64 = S_MOV_B64 0
+ S_BRANCH %bb.3
+
+ bb.2:
+ %1:sreg_64 = S_MOV_B64 -1
+ S_BRANCH %bb.3
+
+ bb.3:
+ %2:sreg_64 = PHI %0:sreg_64, %bb.1, %1:sreg_64, %bb.2
+ S_CBRANCH_SCC1 %bb.7, implicit undef $scc
+ S_BRANCH %bb.4
+
+ bb.8:
+...
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