[PATCH] D62519: AMDGPU: Don't enable all lanes with non-CSR VGPR spills
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 28 06:17:55 PDT 2019
arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
If the only VGPRs used for SGPR spilling were not CSRs, this was
enabling all laness and immediately restoring exec. This is the usual
situation in leaf functions.
https://reviews.llvm.org/D62519
Files:
lib/Target/AMDGPU/SIFrameLowering.cpp
test/CodeGen/AMDGPU/callee-frame-setup.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D62519.201648.patch
Type: text/x-patch
Size: 5053 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190528/b7160927/attachment.bin>
More information about the llvm-commits
mailing list