[PATCH] D60640: AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT

[Tom Stellard via Phabricator via llvm-commits]

tstellar marked an inline comment as done.
tstellar added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:86-87
+
+  // Special case for COPY from the scc register bank.  The scc register bank
+  // is modeled using 32-bit sgprs.
+  const MachineOperand &Src = I.getOperand(1);
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arsenm wrote:
> tstellar wrote:
> > arsenm wrote:
> > > This isn't true, or at least isn't supposed to be. The SCC bank needs to be distinct from a 1-bit value in an SGPR bank
> > When we select scc uses/defs, we need to copy the value from/to an 32-bit sgpr to handle the case where there are 2 scc values live at the same time.
> Do you have an example of this? I think this shouldn't be possible. We don't use SCC in the cases where > 1 use are needed in a single instruction (i.e. and/or/xor)
What I'm talking about is scenarios like the icmp_s_mix testcase in this patch.


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https://reviews.llvm.org/D60640