[PATCH] D62223: [DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2926
+  // Hoist one-use addition by constant:  (x + C) - y  ->  (x - y) + C
+  if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
+      isConstantOrConstantVector(N0.getOperand(1))) {
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lebedev.ri wrote:
> bjope wrote:
> > Not sure if it is super important, or common, in reality. But maybe this should be trigger for an add-like-or as well? 
> > 
> > An ADD with no common bits set in the operands is canonicalized into OR by DAGCombiner, so there could be lots of OR:s out there that really are ADD:s.
> Yes, correct observation. I did think about it when writing,
> but i did not see any easy way to do that here.
> Any suggestions?
We could introduce some helper to make it easier to match an "add-like" node. However, checking "noCommonBitsSet" to detect if an OR is add-like currently involves ValueTracking, so it is not a cheap operation. We probably want to see that we get some payback if doing that, and not just wasting time.

Since we already match on ISD::ADD in several places above, it might have been too much to ask for in this patch. So I think we can save it for later.



Repository:
  rL LLVM

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  https://reviews.llvm.org/D62223/new/

https://reviews.llvm.org/D62223