[PATCH] D62132: [RFC] Intrinsics for Hardware Loops

[Sam Parker via Phabricator via llvm-commits]

samparker updated this revision to Diff 200890.
samparker added a reviewer: hfinkel.
samparker added a comment.
Herald added subscribers: jsji, jfb, kbarton, nemanjai.

Introduced a target independent pass to insert intrinsics to generate hardware loops, which is based upon PPCCTRLoops. A hook has been added to TTI to decide what loops should be converted:

bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,

  AssumptionCache &AC,
  TargetLibraryInfo *LibInfo,
  HardwareLoopInfo &HWLoopInfo);
      

HardwareLoopInfo is introduced to allow the backend to describe the properties of the loop:

      

struct HardwareLoopInfo {

  HardwareLoopInfo(Loop *L) : L(L) { }
  Loop *L                 = nullptr;
  BasicBlock *ExitBlock   = nullptr;
  BranchInst *ExitBranch  = nullptr;
  const SCEV *ExitCount   = nullptr;
  Instruction *Predicate  = nullptr; // Value controlling masked ops.
  IntegerType *CountType  = nullptr;
  bool PerformTest        = false;   // Can guard loop entry.
  bool IsNestingLegal     = false;   // Can HW loops be nested.
  bool InsertPHICounter   = false;   // Keep the loop counter in reg?
  unsigned NumElements    = 1;       // Max number of elements
                                     // processed in an iteration.

};

      

The pass can insert four different intrinsics for setting up a loop:

- int_set_loop_iterations: Takes an integer trip count.
- int_test_set_loop_iterations : Takes an integer trip count and tests whether the loop should be entered.
- int_set_loop_elements : Takes two integers, (1) the total elements to be processed by the loop and (2) the maximum number of elements processed in each iteration.
- int_test_set_loop_elements : Same as above but also tests whether the loop should be entered.

PowerPC codegen tests are still passing and the hacks in the arm backend allow by previous example to still work.

My plan now is:

- Introduce the target independent with just the features (set_loop_iterations and loop_dec) to enable PowerPC and remove PPCTRLoops.
- Add Arm support for the previous two intrinsics.
- Introduce the testing form of set_loop_iterations with Arm support.
- Introduce the 'element' versions of the intrinsics with Arm support.

The Arm support will be dependent on getting the initial architecture support upstream.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62132/new/

https://reviews.llvm.org/D62132

Files:
  include/llvm/Analysis/TargetTransformInfo.h
  include/llvm/Analysis/TargetTransformInfoImpl.h
  include/llvm/CodeGen/BasicTTIImpl.h
  include/llvm/CodeGen/Passes.h
  include/llvm/IR/Intrinsics.td
  include/llvm/InitializePasses.h
  lib/Analysis/TargetTransformInfo.cpp
  lib/CodeGen/CMakeLists.txt
  lib/CodeGen/HardwareLoops.cpp
  lib/Target/ARM/ARM.h
  lib/Target/ARM/ARMFinalizeHardwareLoops.cpp
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrInfo.td
  lib/Target/ARM/ARMInstrThumb2.td
  lib/Target/ARM/ARMRegisterInfo.td
  lib/Target/ARM/ARMTargetMachine.cpp
  lib/Target/ARM/ARMTargetTransformInfo.cpp
  lib/Target/ARM/ARMTargetTransformInfo.h
  lib/Target/ARM/CMakeLists.txt
  lib/Target/PowerPC/PPCCTRLoops.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstr64Bit.td
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCTargetMachine.cpp
  lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  lib/Target/PowerPC/PPCTargetTransformInfo.h
  test/CodeGen/PowerPC/ctrloop-intrin.ll
  test/CodeGen/PowerPC/ppc-passname.ll
  test/CodeGen/Thumb2/mve-tailpred.ll

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