[PATCH] D62266: [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, spatel, rogfer01, efriedma.
lebedev.ri added a project: LLVM.
Herald added subscribers: kristof.beyls, javed.absar.
lebedev.ri added a parent revision: D62263: [DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1  ->  add (xor y, -1), x  fold.

All changes except ARM look **great**.

The regression `test/CodeGen/ARM/addsubcarry-promotion.ll` in the
case of `-mtriple thumbv8m.main` (`THUMB` check prefix) looks like:
old;

  t0: ch = EntryToken
              t6: i32,ch = CopyFromReg t0, Register:i32 %2
            t30: i32 = sub Constant:i32<1>, t6
          t32: i32 = sign_extend_inreg t30, ValueType:ch:i16
            t4: i32,ch = CopyFromReg t0, Register:i32 %1
            t2: i32,ch = CopyFromReg t0, Register:i32 %0
          t29: i32,i32 = uaddo t4, t2
        t39: i32,i32 = addcarry t32, Constant:i32<0>, t29:1
      t38: i32 = and t39, Constant:i32<65535>
    t42: ch = br_cc t0, seteq:ch, t38, Constant:i32<0>, BasicBlock:ch<if.end 0x55af62265538>
  t19: ch = br t42, BasicBlock:ch<for.cond.preheader 0x55af622653a8>

new:

  t0: ch = EntryToken
            t4: i32,ch = CopyFromReg t0, Register:i32 %1
            t2: i32,ch = CopyFromReg t0, Register:i32 %0
          t28: i32,i32 = uaddo t4, t2
          t6: i32,ch = CopyFromReg t0, Register:i32 %2
        t20: i32 = sub t28:1, t6
      t35: i32 = and t20, Constant:i32<65535>
    t37: ch = br_cc t0, seteq:ch, t35, Constant:i32<65535>, BasicBlock:ch<if.end 0x5574d92b1328>
  t19: ch = br t37, BasicBlock:ch<for.cond.preheader 0x5574d92b1198>

So the DAG is simpler, but that particular case is worse for the backend.
I'm not quite sure how to improve this, or how important that is.
Testcase looks overminimized.


Repository:
  rL LLVM

https://reviews.llvm.org/D62266

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/shift-amount-mod.ll
  test/CodeGen/AArch64/sink-addsub-of-const.ll
  test/CodeGen/ARM/addsubcarry-promotion.ll
  test/CodeGen/X86/shift-amount-mod.ll
  test/CodeGen/X86/sink-addsub-of-const.ll

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