[llvm] r361331 - AMDGPU: Assume call pseudos are convergent

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue May 21 16:23:10 2019
New Revision: 361331

URL: http://llvm.org/viewvc/llvm-project?rev=361331&view=rev
Log:
AMDGPU: Assume call pseudos are convergent

There should probably be nonconvergent versions, but my guess is it
doesn't matter in practice.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/tail-duplication-convergent.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=361331&r1=361330&r2=361331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Tue May 21 16:23:10 2019
@@ -383,6 +383,8 @@ def SI_CALL_ISEL : SPseudoInstSI <
   let isCall = 1;
   let SchedRW = [WriteBranch];
   let usesCustomInserter = 1;
+  // TODO: Should really base this on the call target
+  let isConvergent = 1;
 }
 
 // Wrapper around s_swappc_b64 with extra $callee parameter to track
@@ -393,6 +395,8 @@ def SI_CALL : SPseudoInstSI <
   let isCall = 1;
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteBranch];
+  // TODO: Should really base this on the call target
+  let isConvergent = 1;
 }
 
 // Tail call handling pseudo
@@ -406,6 +410,8 @@ def SI_TCRETURN : SPseudoInstSI <(outs),
   let isBarrier = 1;
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteBranch];
+  // TODO: Should really base this on the call target
+  let isConvergent = 1;
 }
 
 

Added: llvm/trunk/test/CodeGen/AMDGPU/tail-duplication-convergent.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/tail-duplication-convergent.ll?rev=361331&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/tail-duplication-convergent.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/tail-duplication-convergent.ll Tue May 21 16:23:10 2019
@@ -0,0 +1,105 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -O2 -tail-dup-size=1000 -tail-dup-placement-threshold=1000 -enable-tail-merge=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+
+; Need to to trigger tail duplication this during
+; MachineBlockPlacement, since calls aren't tail duplicated pre-RA.
+
+declare void @nonconvergent_func() #0
+declare void @convergent_func() #1
+declare void @llvm.amdgcn.s.barrier() #1
+
+; barrier shouldn't be duplicated.
+
+; GCN-LABEL: {{^}}taildup_barrier:
+; GCN: s_barrier
+; GCN-NOT: s_barrier
+define void @taildup_barrier(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #0 {
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, i32 addrspace(1)* %a
+  br label %call
+
+bb2:
+  store i32 1, i32 addrspace(1)* %a
+  br label %call
+
+call:
+  call void @llvm.amdgcn.s.barrier()
+  br label %ret
+
+ret:
+  ret void
+}
+
+; GCN-LABEL: {{^}}taildup_convergent_call:
+; GCN: s_swappc_b64
+; GCN-NOT: s_swappc_b64
+define void @taildup_convergent_call(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, i32 addrspace(1)* %a
+  br label %call
+
+bb2:
+  store i32 1, i32 addrspace(1)* %a
+  br label %call
+
+call:
+  call void @convergent_func()
+  br label %ret
+
+ret:
+  ret void
+}
+
+; TODO: Currently there is only one convergent call pseudo, but this
+; theoretically could use a nonconvergent variant.
+; GCN-LABEL: {{^}}taildup_nonconvergent_call:
+; GCN: s_swappc_b64
+; GCN-NOT: s_swappc_b64
+define void @taildup_nonconvergent_call(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, i32 addrspace(1)* %a
+  br label %call
+
+bb2:
+  store i32 1, i32 addrspace(1)* %a
+  br label %call
+
+call:
+  call void @nonconvergent_func()
+  br label %ret
+
+ret:
+  ret void
+}
+
+; GCN-LABEL: {{^}}taildup_convergent_tailcall:
+; GCN: s_setpc_b64
+; GCN-NOT: s_setpc_b64
+define void @taildup_convergent_tailcall(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, i32 addrspace(1)* %a
+  br label %call
+
+bb2:
+  store i32 1, i32 addrspace(1)* %a
+  br label %call
+
+call:
+  tail call void @convergent_func()
+  ret void
+}
+
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind convergent }