[PATCH] D61887: [SelectionDAG] computeKnownBits - support constant pool values from target

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:5777
 
   auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
   if (!CNode || CNode->isMachineConstantPoolEntry() || CNode->getOffset() != 0)
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Is there an implicit assumption here that constant pool loads won't be a SEXTLOAD/ZEXTLOAD/EXTLOAD? If they were we'd get a mismatch of bitwidth right?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61887/new/

https://reviews.llvm.org/D61887