[PATCH] D62132: [RFC] Intrinsics for Hardware Loops

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

In D62132#1508322 <https://reviews.llvm.org/D62132#1508322>, @SjoerdMeijer wrote:

> Loop tail predication and VPT block predication use different mechanism, architecturally. The former uses FPSCR.LTPSIZE, and the latter VPR, right? But I don't think it matters or changes anything for the rest of your story.


Indeed, the register is only used for code generation here. I expect that we will need separate registers in the compiler for each in the final implementation as both architecture registers are used at runtime if there's a VPT block within a tail-predicated loop.


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