[PATCH] D62132: [RFC] Intrinsics for Hardware Loops

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Hi Sam, many thanks for the detailed RFC and prototype!

Of course I need some more time to digest this, but just a first nitpick of something I noticed:

> To help / enable the lowering of of an i1 vector, the VPR register has been added. This is a status register that contains the P0 predicate and is also used to model the implicit predicates of tail-predicated loops.

Loop tail predication and VPT block predication use different mechanism, architecturally. The former uses FPSCR.LTPSIZE, and the latter VPR, right? But I don't think it matters or changes anything for the rest of your story.


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https://reviews.llvm.org/D62132