[llvm] r361105 - [NFC][AArch64] Autogenerate bitfield-insert.ll, selectcc-to-shiftand.ll tests
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Sat May 18 10:42:07 PDT 2019
Author: lebedevri
Date: Sat May 18 10:42:06 2019
New Revision: 361105
URL: http://llvm.org/viewvc/llvm-project?rev=361105&view=rev
Log:
[NFC][AArch64] Autogenerate bitfield-insert.ll, selectcc-to-shiftand.ll tests
Investigating bit-extract (ubfx) pattern with shifted mask.
Modified:
llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
llvm/trunk/test/CodeGen/AArch64/selectcc-to-shiftand.ll
Modified: llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll?rev=361105&r1=361104&r2=361105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll Sat May 18 10:42:06 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; First, a simple example from Clang. The registers could plausibly be
@@ -7,8 +8,13 @@
define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
; CHECK-LABEL: from_clang:
-; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
-
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #135
+; CHECK-NEXT: and w8, w0, w8
+; CHECK-NEXT: bfi w8, w1, #3, #4
+; CHECK-NEXT: and x9, x0, #0xffffff00
+; CHECK-NEXT: orr x0, x8, x9
+; CHECK-NEXT: ret
entry:
%f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0
%tmp.sroa.0.0.extract.trunc = trunc i64 %f.coerce.fca.0.extract to i32
@@ -25,9 +31,12 @@ entry:
define void @test_whole32(i32* %existing, i32* %new) {
; CHECK-LABEL: test_whole32:
-
-; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: bfi w8, w9, #26, #5
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
@@ -43,10 +52,12 @@ define void @test_whole32(i32* %existing
define void @test_whole64(i64* %existing, i64* %new) {
; CHECK-LABEL: test_whole64:
-; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
-; CHECK-NOT: and
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ldr x9, [x1]
+; CHECK-NEXT: bfi x8, x9, #26, #14
+; CHECK-NEXT: str x8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i64, i64* %existing
%oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL
@@ -62,12 +73,13 @@ define void @test_whole64(i64* %existing
define void @test_whole32_from64(i64* %existing, i64* %new) {
; CHECK-LABEL: test_whole32_from64:
-
-
-; CHECK: bfxil {{x[0-9]+}}, {{x[0-9]+}}, #0, #16
-
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ldr x9, [x1]
+; CHECK-NEXT: and x8, x8, #0xffff0000
+; CHECK-NEXT: bfxil x8, x9, #0, #16
+; CHECK-NEXT: str x8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i64, i64* %existing
%oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000
@@ -82,10 +94,14 @@ define void @test_whole32_from64(i64* %e
define void @test_32bit_masked(i32 *%existing, i32 *%new) {
; CHECK-LABEL: test_32bit_masked:
-
-; CHECK: and
-; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: mov w10, #135
+; CHECK-NEXT: and w8, w8, w10
+; CHECK-NEXT: bfi w8, w9, #3, #4
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 135 ; = 0x87
@@ -101,9 +117,13 @@ define void @test_32bit_masked(i32 *%exi
define void @test_64bit_masked(i64 *%existing, i64 *%new) {
; CHECK-LABEL: test_64bit_masked:
-; CHECK: and
-; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ldr x9, [x1]
+; CHECK-NEXT: and x8, x8, #0xff00000000
+; CHECK-NEXT: bfi x8, x9, #40, #8
+; CHECK-NEXT: str x8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i64, i64* %existing
%oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000
@@ -120,10 +140,14 @@ define void @test_64bit_masked(i64 *%exi
; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
; CHECK-LABEL: test_32bit_complexmask:
-
-; CHECK: and
-; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: mov w10, #647
+; CHECK-NEXT: and w8, w8, w10
+; CHECK-NEXT: bfi w8, w9, #3, #4
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 647 ; = 0x287
@@ -140,10 +164,16 @@ define void @test_32bit_complexmask(i32
; Neither mask is a contiguous set of 1s. BFI can't be used
define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
; CHECK-LABEL: test_32bit_badmask:
-; CHECK-NOT: bfi
-; CHECK-NOT: bfm
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: mov w10, #135
+; CHECK-NEXT: mov w11, #632
+; CHECK-NEXT: and w8, w8, w10
+; CHECK-NEXT: and w9, w11, w9, lsl #3
+; CHECK-NEXT: orr w8, w8, w9
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 135 ; = 0x87
@@ -160,10 +190,17 @@ define void @test_32bit_badmask(i32 *%ex
; Ditto
define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
; CHECK-LABEL: test_64bit_badmask:
-; CHECK-NOT: bfi
-; CHECK-NOT: bfm
-; CHECK: ret
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x0]
+; CHECK-NEXT: ldr x9, [x1]
+; CHECK-NEXT: mov w10, #135
+; CHECK-NEXT: and x8, x8, x10
+; CHECK-NEXT: lsl w9, w9, #3
+; CHECK-NEXT: mov w10, #664
+; CHECK-NEXT: and x9, x9, x10
+; CHECK-NEXT: orr x8, x8, x9
+; CHECK-NEXT: str x8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i64, i64* %existing
%oldval_keep = and i64 %oldval, 135 ; = 0x87
@@ -181,7 +218,13 @@ define void @test_64bit_badmask(i64 *%ex
; (e.g. result of str.bf1 = str.bf2)
define void @test_32bit_with_shr(i32* %existing, i32* %new) {
; CHECK-LABEL: test_32bit_with_shr:
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: lsr w9, w9, #14
+; CHECK-NEXT: bfi w8, w9, #26, #5
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
@@ -191,8 +234,6 @@ define void @test_32bit_with_shr(i32* %e
%combined = or i32 %oldval_keep, %newval_masked
store volatile i32 %combined, i32* %existing
-; CHECK: lsr [[BIT:w[0-9]+]], {{w[0-9]+}}, #14
-; CHECK: bfi {{w[0-9]+}}, [[BIT]], #26, #5
ret void
}
@@ -200,7 +241,13 @@ define void @test_32bit_with_shr(i32* %e
; Bitfield insert where the second or operand is a better match to be folded into the BFM
define void @test_32bit_opnd1_better(i32* %existing, i32* %new) {
; CHECK-LABEL: test_32bit_opnd1_better:
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: ldr w9, [x1]
+; CHECK-NEXT: and w8, w8, #0xffff
+; CHECK-NEXT: bfi w8, w9, #16, #8
+; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: ret
%oldval = load volatile i32, i32* %existing
%oldval_keep = and i32 %oldval, 65535 ; 0x0000ffff
@@ -210,8 +257,6 @@ define void @test_32bit_opnd1_better(i32
%combined = or i32 %oldval_keep, %newval_masked
store volatile i32 %combined, i32* %existing
-; CHECK: and [[BIT:w[0-9]+]], {{w[0-9]+}}, #0xffff
-; CHECK: bfi [[BIT]], {{w[0-9]+}}, #16, #8
ret void
}
@@ -219,12 +264,14 @@ define void @test_32bit_opnd1_better(i32
; Tests when all the bits from one operand are not useful
define i32 @test_nouseful_bits(i8 %a, i32 %b) {
; CHECK-LABEL: test_nouseful_bits:
-; CHECK: bfi
-; CHECK: bfi
-; CHECK: bfi
-; CHECK-NOT: bfi
-; CHECK-NOT: or
-; CHECK: lsl
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, w0
+; CHECK-NEXT: bfi w8, w8, #8, #24
+; CHECK-NEXT: mov w9, w0
+; CHECK-NEXT: bfi w9, w8, #8, #24
+; CHECK-NEXT: bfi w0, w9, #8, #24
+; CHECK-NEXT: lsl w0, w0, #8
+; CHECK-NEXT: ret
%conv = zext i8 %a to i32 ; 0 0 0 A
%shl = shl i32 %b, 8 ; B2 B1 B0 0
%or = or i32 %conv, %shl ; B2 B1 B0 A
@@ -239,13 +286,13 @@ define i32 @test_nouseful_bits(i8 %a, i3
}
define void @test_nouseful_strb(i32* %ptr32, i8* %ptr8, i32 %x) {
+; CHECK-LABEL: test_nouseful_strb:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: bfxil w8, w2, #16, #3
+; CHECK-NEXT: strb w8, [x1]
+; CHECK-NEXT: ret
entry:
-; CHECK-LABEL: @test_nouseful_strb
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8
-; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3
-; CHECK-NEXT: strb [[REG1]],
-; CHECK-NEXT: ret
%0 = load i32, i32* %ptr32, align 8
%and = and i32 %0, -8
%shr = lshr i32 %x, 16
@@ -257,13 +304,13 @@ entry:
}
define void @test_nouseful_strh(i32* %ptr32, i16* %ptr16, i32 %x) {
+; CHECK-LABEL: test_nouseful_strh:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: bfxil w8, w2, #16, #4
+; CHECK-NEXT: strh w8, [x1]
+; CHECK-NEXT: ret
entry:
-; CHECK-LABEL: @test_nouseful_strh
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0
-; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4
-; CHECK-NEXT: strh [[REG1]],
-; CHECK-NEXT: ret
%0 = load i32, i32* %ptr32, align 8
%and = and i32 %0, -16
%shr = lshr i32 %x, 16
@@ -275,13 +322,13 @@ entry:
}
define void @test_nouseful_sturb(i32* %ptr32, i8* %ptr8, i32 %x) {
+; CHECK-LABEL: test_nouseful_sturb:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: bfxil w8, w2, #16, #3
+; CHECK-NEXT: sturb w8, [x1, #-1]
+; CHECK-NEXT: ret
entry:
-; CHECK-LABEL: @test_nouseful_sturb
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8
-; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3
-; CHECK-NEXT: sturb [[REG1]],
-; CHECK-NEXT: ret
%0 = load i32, i32* %ptr32, align 8
%and = and i32 %0, -8
%shr = lshr i32 %x, 16
@@ -294,13 +341,13 @@ entry:
}
define void @test_nouseful_sturh(i32* %ptr32, i16* %ptr16, i32 %x) {
+; CHECK-LABEL: test_nouseful_sturh:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: bfxil w8, w2, #16, #4
+; CHECK-NEXT: sturh w8, [x1, #-2]
+; CHECK-NEXT: ret
entry:
-; CHECK-LABEL: @test_nouseful_sturh
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0
-; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4
-; CHECK-NEXT: sturh [[REG1]],
-; CHECK-NEXT: ret
%0 = load i32, i32* %ptr32, align 8
%and = and i32 %0, -16
%shr = lshr i32 %x, 16
@@ -316,10 +363,12 @@ entry:
; (and Y, Mask1Imm)' iff Mask0Imm and ~Mask1Imm are equivalent and one of the
; MaskImms is a shifted mask (e.g., 0x000ffff0).
-; CHECK-LABEL: @test_or_and_and1
-; CHECK: lsr w8, w1, #4
-; CHECK: bfi w0, w8, #4, #12
define i32 @test_or_and_and1(i32 %a, i32 %b) {
+; CHECK-LABEL: test_or_and_and1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr w8, w1, #4
+; CHECK-NEXT: bfi w0, w8, #4, #12
+; CHECK-NEXT: ret
entry:
%and = and i32 %a, -65521 ; 0xffff000f
%and1 = and i32 %b, 65520 ; 0x0000fff0
@@ -327,10 +376,13 @@ entry:
ret i32 %or
}
-; CHECK-LABEL: @test_or_and_and2
-; CHECK: lsr w8, w0, #4
-; CHECK: bfi w1, w8, #4, #12
define i32 @test_or_and_and2(i32 %a, i32 %b) {
+; CHECK-LABEL: test_or_and_and2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr w8, w0, #4
+; CHECK-NEXT: bfi w1, w8, #4, #12
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
entry:
%and = and i32 %a, 65520 ; 0x0000fff0
%and1 = and i32 %b, -65521 ; 0xffff000f
@@ -338,10 +390,12 @@ entry:
ret i32 %or
}
-; CHECK-LABEL: @test_or_and_and3
-; CHECK: lsr x8, x1, #16
-; CHECK: bfi x0, x8, #16, #32
define i64 @test_or_and_and3(i64 %a, i64 %b) {
+; CHECK-LABEL: test_or_and_and3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr x8, x1, #16
+; CHECK-NEXT: bfi x0, x8, #16, #32
+; CHECK-NEXT: ret
entry:
%and = and i64 %a, -281474976645121 ; 0xffff00000000ffff
%and1 = and i64 %b, 281474976645120 ; 0x0000ffffffff0000
@@ -350,12 +404,14 @@ entry:
}
; Don't convert 'and' with multiple uses.
-; CHECK-LABEL: @test_or_and_and4
-; CHECK: and w8, w0, #0xffff000f
-; CHECK: and w9, w1, #0xfff0
-; CHECK: orr w0, w9, w8
-; CHECK: str w8, [x2
define i32 @test_or_and_and4(i32 %a, i32 %b, i32* %ptr) {
+; CHECK-LABEL: test_or_and_and4:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and w8, w0, #0xffff000f
+; CHECK-NEXT: and w9, w1, #0xfff0
+; CHECK-NEXT: orr w0, w9, w8
+; CHECK-NEXT: str w8, [x2]
+; CHECK-NEXT: ret
entry:
%and = and i32 %a, -65521
store i32 %and, i32* %ptr, align 4
@@ -365,12 +421,14 @@ entry:
}
; Don't convert 'and' with multiple uses.
-; CHECK-LABEL: @test_or_and_and5
-; CHECK: and w8, w1, #0xfff0
-; CHECK: and w9, w0, #0xffff000f
-; CHECK: orr w0, w8, w9
-; CHECK: str w8, [x2]
define i32 @test_or_and_and5(i32 %a, i32 %b, i32* %ptr) {
+; CHECK-LABEL: test_or_and_and5:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and w8, w1, #0xfff0
+; CHECK-NEXT: and w9, w0, #0xffff000f
+; CHECK-NEXT: orr w0, w8, w9
+; CHECK-NEXT: str w8, [x2]
+; CHECK-NEXT: ret
entry:
%and = and i32 %b, 65520
store i32 %and, i32* %ptr, align 4
@@ -379,47 +437,57 @@ entry:
ret i32 %or
}
-; CHECK-LABEL: @test1
-; CHECK: mov [[REG:w[0-9]+]], #5
-; CHECK: bfxil w0, [[REG]], #0, #4
define i32 @test1(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: bfxil w0, w8, #0, #4
+; CHECK-NEXT: ret
%1 = and i32 %a, -16 ; 0xfffffff0
%2 = or i32 %1, 5 ; 0x00000005
ret i32 %2
}
-; CHECK-LABEL: @test2
-; CHECK: mov [[REG:w[0-9]+]], #10
-; CHECK: bfi w0, [[REG]], #22, #4
define i32 @test2(i32 %a) {
+; CHECK-LABEL: test2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: bfi w0, w8, #22, #4
+; CHECK-NEXT: ret
%1 = and i32 %a, -62914561 ; 0xfc3fffff
%2 = or i32 %1, 41943040 ; 0x06400000
ret i32 %2
}
-; CHECK-LABEL: @test3
-; CHECK: mov [[REG:x[0-9]+]], #5
-; CHECK: bfxil x0, [[REG]], #0, #3
define i64 @test3(i64 %a) {
+; CHECK-LABEL: test3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #5
+; CHECK-NEXT: bfxil x0, x8, #0, #3
+; CHECK-NEXT: ret
%1 = and i64 %a, -8 ; 0xfffffffffffffff8
%2 = or i64 %1, 5 ; 0x0000000000000005
ret i64 %2
}
-; CHECK-LABEL: @test4
-; CHECK: mov [[REG:x[0-9]+]], #9
-; CHECK: bfi x0, [[REG]], #1, #7
define i64 @test4(i64 %a) {
+; CHECK-LABEL: test4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #9
+; CHECK-NEXT: bfi x0, x8, #1, #7
+; CHECK-NEXT: ret
%1 = and i64 %a, -255 ; 0xffffffffffffff01
%2 = or i64 %1, 18 ; 0x0000000000000012
ret i64 %2
}
; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR.
-; CHECK-LABEL: @test5
-; CHECK: and [[REG:w[0-9]+]], w0, #0xfffffff0
-; CHECK: orr w0, [[REG]], #0x6
define i32 @test5(i32 %a) {
+; CHECK-LABEL: test5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w0, #0xfffffff0
+; CHECK-NEXT: orr w0, w8, #0x6
+; CHECK-NEXT: ret
%1 = and i32 %a, 4294967280 ; 0xfffffff0
%2 = or i32 %1, 6 ; 0x00000006
ret i32 %2
@@ -427,11 +495,13 @@ define i32 @test5(i32 %a) {
; BFXIL will use the same constant as the ORR, so we don't care how the constant
; is materialized (it's an equal cost either way).
-; CHECK-LABEL: @test6
-; CHECK: mov [[REG:w[0-9]+]], #23250
-; CHECK: movk [[REG]], #11, lsl #16
-; CHECK: bfxil w0, [[REG]], #0, #20
define i32 @test6(i32 %a) {
+; CHECK-LABEL: test6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #23250
+; CHECK-NEXT: movk w8, #11, lsl #16
+; CHECK-NEXT: bfxil w0, w8, #0, #20
+; CHECK-NEXT: ret
%1 = and i32 %a, 4293918720 ; 0xfff00000
%2 = or i32 %1, 744146 ; 0x000b5ad2
ret i32 %2
@@ -439,11 +509,13 @@ define i32 @test6(i32 %a) {
; BFIs that require the same number of instruction to materialize the constant
; as the original ORR are okay.
-; CHECK-LABEL: @test7
-; CHECK: mov [[REG:w[0-9]+]], #44393
-; CHECK: movk [[REG]], #5, lsl #16
-; CHECK: bfi w0, [[REG]], #1, #19
define i32 @test7(i32 %a) {
+; CHECK-LABEL: test7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #44393
+; CHECK-NEXT: movk w8, #5, lsl #16
+; CHECK-NEXT: bfi w0, w8, #1, #19
+; CHECK-NEXT: ret
%1 = and i32 %a, 4293918721 ; 0xfff00001
%2 = or i32 %1, 744146 ; 0x000b5ad2
ret i32 %2
@@ -453,12 +525,14 @@ define i32 @test7(i32 %a) {
; to the original ORR are not okay. In this case we would be replacing the
; 'and' with a 'movk', which would decrease ILP while using the same number of
; instructions.
-; CHECK-LABEL: @test8
-; CHECK: mov [[REG2:x[0-9]+]], #2035482624
-; CHECK: and [[REG1:x[0-9]+]], x0, #0xff000000000000ff
-; CHECK: movk [[REG2]], #36694, lsl #32
-; CHECK: orr x0, [[REG1]], [[REG2]]
define i64 @test8(i64 %a) {
+; CHECK-LABEL: test8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x9, #2035482624
+; CHECK-NEXT: and x8, x0, #0xff000000000000ff
+; CHECK-NEXT: movk x9, #36694, lsl #32
+; CHECK-NEXT: orr x0, x8, x9
+; CHECK-NEXT: ret
%1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff
%2 = or i64 %1, 157601565442048 ; 0x00008f5679530000
ret i64 %2
@@ -468,11 +542,14 @@ define i64 @test8(i64 %a) {
; that is expected to catch this case is unable to deal with the trunc, which
; results in a failing check due to a mismatch between the BFI opcode and
; the expected value type of the OR.
-; CHECK-LABEL: @test9
-; CHECK: lsr x0, x0, #12
-; CHECK: lsr [[REG:w[0-9]+]], w1, #23
-; CHECK: bfi w0, [[REG]], #23, #9
define i32 @test9(i64 %b, i32 %e) {
+; CHECK-LABEL: test9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr x0, x0, #12
+; CHECK-NEXT: lsr w8, w1, #23
+; CHECK-NEXT: bfi w0, w8, #23, #9
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
%c = lshr i64 %b, 12
%d = trunc i64 %c to i32
%f = and i32 %d, 8388607
@@ -481,11 +558,13 @@ define i32 @test9(i64 %b, i32 %e) {
ret i32 %h
}
-; CHECK-LABEL: test_complex_type:
-; CHECK: ldr d0, [x0], #8
-; CHECK: orr [[BOTH:x[0-9]+]], x0, x1, lsl #32
-; CHECK: str [[BOTH]], [x2]
define <2 x i32> @test_complex_type(<2 x i32>* %addr, i64 %in, i64* %bf ) {
+; CHECK-LABEL: test_complex_type:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0], #8
+; CHECK-NEXT: orr x8, x0, x1, lsl #32
+; CHECK-NEXT: str x8, [x2]
+; CHECK-NEXT: ret
%vec = load <2 x i32>, <2 x i32>* %addr
%vec.next = getelementptr <2 x i32>, <2 x i32>* %addr, i32 1
Modified: llvm/trunk/test/CodeGen/AArch64/selectcc-to-shiftand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/selectcc-to-shiftand.ll?rev=361105&r1=361104&r2=361105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/selectcc-to-shiftand.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/selectcc-to-shiftand.ll Sat May 18 10:42:06 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; Compare if negative and select of constants where one constant is zero.
@@ -8,7 +9,6 @@ define i32 @neg_sel_constants(i32 %a) {
; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: and w0, w8, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp.1 = icmp slt i32 %a, 0
%retval = select i1 %tmp.1, i32 5, i32 0
ret i32 %retval
@@ -22,7 +22,6 @@ define i32 @neg_sel_special_constant(i32
; CHECK-NEXT: lsr w8, w0, #22
; CHECK-NEXT: and w0, w8, #0x200
; CHECK-NEXT: ret
-;
%tmp.1 = icmp slt i32 %a, 0
%retval = select i1 %tmp.1, i32 512, i32 0
ret i32 %retval
@@ -35,7 +34,6 @@ define i32 @neg_sel_variable_and_zero(i3
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w1, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp.1 = icmp slt i32 %a, 0
%retval = select i1 %tmp.1, i32 %b, i32 0
ret i32 %retval
@@ -48,7 +46,6 @@ define i32 @not_pos_sel_same_variable(i3
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp = icmp slt i32 %a, 1
%min = select i1 %tmp, i32 %a, i32 0
ret i32 %min
@@ -64,7 +61,6 @@ define i32 @pos_sel_constants(i32 %a) {
; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: bic w0, w8, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp.1 = icmp sgt i32 %a, -1
%retval = select i1 %tmp.1, i32 5, i32 0
ret i32 %retval
@@ -78,7 +74,6 @@ define i32 @pos_sel_special_constant(i32
; CHECK-NEXT: mov w8, #512
; CHECK-NEXT: bic w0, w8, w0, lsr #22
; CHECK-NEXT: ret
-;
%tmp.1 = icmp sgt i32 %a, -1
%retval = select i1 %tmp.1, i32 512, i32 0
ret i32 %retval
@@ -91,7 +86,6 @@ define i32 @pos_sel_variable_and_zero(i3
; CHECK: // %bb.0:
; CHECK-NEXT: bic w0, w1, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp.1 = icmp sgt i32 %a, -1
%retval = select i1 %tmp.1, i32 %b, i32 0
ret i32 %retval
@@ -104,7 +98,6 @@ define i32 @not_neg_sel_same_variable(i3
; CHECK: // %bb.0:
; CHECK-NEXT: bic w0, w0, w0, asr #31
; CHECK-NEXT: ret
-;
%tmp = icmp sgt i32 %a, 0
%min = select i1 %tmp, i32 %a, i32 0
ret i32 %min
@@ -119,7 +112,6 @@ define i32 @PR31175(i32 %x, i32 %y) {
; CHECK-NEXT: sub w8, w0, w1
; CHECK-NEXT: bic w0, w8, w8, asr #31
; CHECK-NEXT: ret
-;
%sub = sub nsw i32 %x, %y
%cmp = icmp sgt i32 %sub, 0
%sel = select i1 %cmp, i32 %sub, i32 0
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