[PATCH] D61515: [AArch64][SVE2] Asm: add SQRDMLAH/SQRDMLSH instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.


================
Comment at: test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s:8
+sqrdmlah z0.h, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrdmlah z0.h, z1.h, z8.h[0]
----------------
c-rhodes wrote:
> rovka wrote:
> > Why not "error: Invalid restricted vector register, expected z0.h..z7.h" ?
> This is being parsed as the vector form of the instruction where everything until the index is invalid, I guess it's hitting that error first. I agree it's a poor diagnostic, I'll see if this can be improved.
I understand what's happening here a bit better now, the debug output from asm-matcher explains it pretty well:

```
Trying to match opcode SQRDMLAH_ZZZ_H
  Matching formal operand class MCK_SVEVectorHReg against actual operand at index 1 (<register 245>): match success using generic matcher
  Matching formal operand class MCK_SVEVectorHReg against actual operand at index 2 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEVectorHReg against actual operand at index 3 (<register 253>): match success using generic matcher
  Matching formal operand class InvalidMatchClass against actual operand at index 4 (<vectorindex 0>): Opcode result: multiple operand mismatches, ignoring this opcode
...
Trying to match opcode SQRDMLAH_ZZZI_H
  Matching formal operand class MCK_SVEVectorHReg against actual operand at index 1 (<register 245>): match success using generic matcher
  Matching formal operand class MCK_SVEVectorHReg against actual operand at index 2 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEVector3bHReg against actual operand at index 3 (<register 253>): Opcode result: multiple operand mismatches, ignoring this opcode
```

The asm-matcher finds no match for this instruction, and in `MatchInstructionImpl` the default result is invalid operand:
```
  // Some state to try to produce better error messages.
  unsigned RetCode = Match_InvalidOperand;
```

This isn't new to SVE2, the same diagnostic is given for SVE instructions that have unpredicated and indexed forms, for instance SDOT. The following is from `sdot-diagnostics.s`:
```
// ------------------------------------------------------------------------- //
// Invalid restricted register for indexed vector.

sdot  z0.s, z1.b, z8.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sdot  z0.s, z1.b, z8.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
```

I'm not sure what can be done from TableGen to improve this


Repository:
  rL LLVM

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  https://reviews.llvm.org/D61515/new/

https://reviews.llvm.org/D61515