[PATCH] D61622: [FastISel][X86] If selectFNeg fails, fall back to SelectionDAG not treating it as an fsub.

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL360111: [FastISel][X86] If selectFNeg fails, fall back to SelectionDAG not treating it… (authored by ctopper, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D61622?vs=198369&id=198392#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61622/new/

https://reviews.llvm.org/D61622

Files:
  llvm/trunk/include/llvm/CodeGen/FastISel.h
  llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll


Index: llvm/trunk/include/llvm/CodeGen/FastISel.h
===================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h
@@ -527,7 +527,7 @@
   /// Select and emit code for a binary operator instruction, which has
   /// an opcode which directly corresponds to the given ISD opcode.
   bool selectBinaryOp(const User *I, unsigned ISDOpcode);
-  bool selectFNeg(const User *I);
+  bool selectFNeg(const User *I, const Value *In);
   bool selectGetElementPtr(const User *I);
   bool selectStackmap(const CallInst *I);
   bool selectPatchpoint(const CallInst *I);
Index: llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
+++ llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=i686-- -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
+; RUN: llc < %s -fast-isel -mtriple=i686-- -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
 
 define double @doo(double %x) nounwind {
 ; CHECK-LABEL: doo:
@@ -65,7 +65,7 @@
 ; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT:    subsd (%ecx), %xmm0
+; SSE2-NEXT:    xorps {{\.LCPI.*}}, %xmm0
 ; SSE2-NEXT:    movsd %xmm0, (%eax)
 ; SSE2-NEXT:    retl
   %a = load double, double* %x
Index: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1712,14 +1712,11 @@
 }
 
 /// Emit an FNeg operation.
-bool FastISel::selectFNeg(const User *I) {
-  Value *X;
-  if (!match(I, m_FNeg(m_Value(X))))
-    return false;
-  unsigned OpReg = getRegForValue(X);
+bool FastISel::selectFNeg(const User *I, const Value *In) {
+  unsigned OpReg = getRegForValue(In);
   if (!OpReg)
     return false;
-  bool OpRegIsKill = hasTrivialKill(X);
+  bool OpRegIsKill = hasTrivialKill(In);
 
   // If the target has ISD::FNEG, use it.
   EVT VT = TLI.getValueType(DL, I->getType());
@@ -1806,9 +1803,13 @@
     return selectBinaryOp(I, ISD::FADD);
   case Instruction::Sub:
     return selectBinaryOp(I, ISD::SUB);
-  case Instruction::FSub: 
+  case Instruction::FSub: {
     // FNeg is currently represented in LLVM IR as a special case of FSub.
-    return selectFNeg(I) || selectBinaryOp(I, ISD::FSUB);
+    Value *X;
+    if (match(I, m_FNeg(m_Value(X))))
+       return selectFNeg(I, X);
+    return selectBinaryOp(I, ISD::FSUB);
+  }
   case Instruction::Mul:
     return selectBinaryOp(I, ISD::MUL);
   case Instruction::FMul:


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