[llvm] r359894 - AMDGPU: Remove redundant patterns for sub

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri May  3 08:08:35 2019
New Revision: 359894

URL: http://llvm.org/viewvc/llvm-project?rev=359894&view=rev
Log:
AMDGPU: Remove redundant patterns for sub

There were 2 patterns for sub, one selecting to sub and one to
subrev. Only one of these will succeed, so remove the reversed one.

Modified:
    llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=359894&r1=359893&r2=359894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Fri May  3 08:08:35 2019
@@ -528,16 +528,12 @@ let AddedComplexity = 1 in {
 let SubtargetPredicate = HasAddNoCarryInsts in {
   def : DivergentBinOp<add, V_ADD_U32_e32>;
   def : DivergentBinOp<sub, V_SUB_U32_e32>;
-  def : DivergentBinOp<sub, V_SUBREV_U32_e32>;
 }
 
 let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
 def : DivergentBinOp<add, V_ADD_I32_e32>;
-
 def : DivergentBinOp<sub, V_SUB_I32_e32>;
 
-def : DivergentBinOp<sub, V_SUBREV_I32_e32>;
-
 def : DivergentBinOp<srl, V_LSHRREV_B32_e32>;
 def : DivergentBinOp<sra, V_ASHRREV_I32_e32>;
 def : DivergentBinOp<shl, V_LSHLREV_B32_e32>;