[llvm] r359768 - [ARM GlobalISel] Select extensions to < 32 bits
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu May 2 02:28:00 PDT 2019
Author: rovka
Date: Thu May 2 02:28:00 2019
New Revision: 359768
URL: http://llvm.org/viewvc/llvm-project?rev=359768&view=rev
Log:
[ARM GlobalISel] Select extensions to < 32 bits
Select G_SEXT and G_ZEXT with destination types smaller than 32 bits in
the exact same way as 32 bits. This overwrites the higher bits, but that
should be ok since all legal users of types smaller than 32 bits ignore
those bits anyway.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=359768&r1=359767&r2=359768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Thu May 2 02:28:00 2019
@@ -862,11 +862,8 @@ bool ARMInstructionSelector::select(Mach
LLVM_FALLTHROUGH;
case G_ZEXT: {
LLT DstTy = MRI.getType(I.getOperand(0).getReg());
- // FIXME: Smaller destination sizes coming soon!
- if (DstTy.getSizeInBits() != 32) {
- LLVM_DEBUG(dbgs() << "Unsupported destination size for extension");
- return false;
- }
+ assert(DstTy.getSizeInBits() <= 32 &&
+ "Unsupported destination size for extension");
LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
unsigned SrcSize = SrcTy.getSizeInBits();
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=359768&r1=359767&r2=359768&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu May 2 02:28:00 2019
@@ -7,6 +7,18 @@
define void @test_trunc_and_anyext_s8_to_s32() { ret void }
define void @test_trunc_and_anyext_s16_to_s32() { ret void }
+ define void @test_trunc_and_zext_s1_to_s16() { ret void }
+ define void @test_trunc_and_sext_s1_to_s16() { ret void }
+ define void @test_trunc_and_anyext_s1_to_s16() { ret void }
+
+ define void @test_trunc_and_zext_s8_to_s16() { ret void }
+ define void @test_trunc_and_sext_s8_to_s16() { ret void }
+ define void @test_trunc_and_anyext_s8_to_s16() { ret void }
+
+ define void @test_trunc_and_zext_s1_to_s8() { ret void }
+ define void @test_trunc_and_sext_s1_to_s8() { ret void }
+ define void @test_trunc_and_anyext_s1_to_s8() { ret void }
+
define void @test_add_s32() { ret void }
define void @test_add_fold_imm_s32() { ret void }
define void @test_add_no_fold_imm_s32() #2 { ret void }
@@ -229,6 +241,314 @@ body: |
; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
+name: test_trunc_and_zext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ZEXT %2(s1)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_SEXT %2(s1)
+ ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ANYEXT %2(s1)
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_zext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
+
+ %3(s16) = G_ZEXT %2(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTB [[VREGTRUNC]], 0, 14, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
+
+ %3(s16) = G_SEXT %2(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ANYEXT %2(s8)
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_zext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_ZEXT %2(s1)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = ANDri [[VREG]], 1, 14, $noreg, $noreg
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_SEXT %2(s1)
+ ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_ANYEXT %2(s1)
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: [[RVREG:%[0-9]+]]:gprnopc = COPY [[VREG]]
+ ; CHECK: STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: true
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir?rev=359768&r1=359767&r2=359768&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir Thu May 2 02:28:00 2019
@@ -11,6 +11,18 @@
define void @test_trunc_and_zext_s16_to_s32() { ret void }
define void @test_trunc_and_sext_s16_to_s32() { ret void }
define void @test_trunc_and_anyext_s16_to_s32() { ret void }
+
+ define void @test_trunc_and_zext_s1_to_s16() { ret void }
+ define void @test_trunc_and_sext_s1_to_s16() { ret void }
+ define void @test_trunc_and_anyext_s1_to_s16() { ret void }
+
+ define void @test_trunc_and_zext_s8_to_s16() { ret void }
+ define void @test_trunc_and_sext_s8_to_s16() { ret void }
+ define void @test_trunc_and_anyext_s8_to_s16() { ret void }
+
+ define void @test_trunc_and_zext_s1_to_s8() { ret void }
+ define void @test_trunc_and_sext_s1_to_s8() { ret void }
+ define void @test_trunc_and_anyext_s1_to_s8() { ret void }
...
---
name: test_trunc_and_zext_s1_to_s32
@@ -286,3 +298,317 @@ body: |
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...
+---
+name: test_trunc_and_zext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ZEXT %2(s1)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_SEXT %2(s1)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s1_to_s16
+# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ANYEXT %2(s1)
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: t2STRHi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_zext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+ ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
+
+ %3(s16) = G_ZEXT %2(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+ ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
+
+ %3(s16) = G_SEXT %2(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s8_to_s16
+# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s8) = G_TRUNC %1(s32)
+
+ %3(s16) = G_ANYEXT %2(s8)
+
+ G_STORE %3(s16), %0(p0) :: (store 2)
+ ; CHECK: [[VREGR:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: t2STRHi12 [[VREGR]], [[PTR]], 0, 14, $noreg :: (store 2)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_zext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_ZEXT %2(s1)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_sext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_SEXT %2(s1)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
+---
+name: test_trunc_and_anyext_s1_to_s8
+# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
+
+ %2(s1) = G_TRUNC %1(s32)
+
+ %3(s8) = G_ANYEXT %2(s1)
+
+ G_STORE %3(s8), %0(p0) :: (store 1)
+ ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
+ ; CHECK: t2STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
+
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
+...
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