[PATCH] D61262: [AArch64] Implement MC support for Scalable Vector Extension 2 (SVE2)

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

@SjoerdMeijer Yes the patch is indeed quite substantial in size :) In contrast to the original SVE MC patches though, these changes are only new TableGen instruction definitions and encoding classes, corresponding (dis)assembler tests and a few flags. For example, there aren't any code changes to e.g. implement/parse new operand types.

We weren't sure if anyone would actually be interested in reviewing the encodings in detail and figured it may be more of a reference we could point to for those in the LLVM community that follow the work on AArch64's Scalable Vector Extensions and are interested in the instructions added in SVE2. Perhaps that would have been worth a comment in the summary/description :)

The encodings have been quite extensively tested and independently verified.

If you still think there is an argument to split up the patch for reviewing purposes, naturally we'd be happy to do so!


Repository:
  rL LLVM

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  https://reviews.llvm.org/D61262/new/

https://reviews.llvm.org/D61262