[PATCH] D60854: [DAGLegalize][PowerPC] Add promote legalization of addc/adde and subc/sube

[Zixuan Wu via Phabricator via llvm-commits]

wuzish updated this revision to Diff 196573.
wuzish marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60854/new/

https://reviews.llvm.org/D60854

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/PowerPC/pr39815.ll
  llvm/test/CodeGen/PowerPC/pr40922.ll


Index: llvm/test/CodeGen/PowerPC/pr40922.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr40922.ll
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s
+
+; Test case adapted from PR40922.
+
+ at a.b = internal global i32 0, align 4
+
+define i32 @a() {
+entry:
+  %call = tail call i32 bitcast (i32 (...)* @d to i32 ()*)()
+  %0 = load i32, i32* @a.b, align 4
+  %conv = zext i32 %0 to i64
+  %add = add nuw nsw i64 %conv, 6
+  %and = and i64 %add, 8589934575
+  %cmp = icmp ult i64 %and, %conv
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %call3 = tail call i32 bitcast (i32 (...)* @e to i32 ()*)()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  store i32 %call, i32* @a.b, align 4
+  ret i32 undef
+}
+
+declare i32 @d(...)
+
+declare i32 @e(...)
Index: llvm/test/CodeGen/PowerPC/pr39815.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr39815.ll
+++ llvm/test/CodeGen/PowerPC/pr39815.ll
@@ -20,10 +20,9 @@
 ; CHECK:      # %bb.0:
 ; CHECK-DAG:   addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc at ha
 ; CHECK-DAG:   ld [[REG3:[0-9]+]], [[VAR1]]@toc at l([[REG1]])
-; CHECK-DAG:   lbz [[REG4:[0-9]+]], 0([[REG3]])
+; CHECK-DAG:   lwz [[REG4:[0-9]+]], 0([[REG3]])
 ; CHECK-DAG:   addic [[REG5:[0-9]+]], [[REG3]], -1
-; CHECK-DAG:   extsb [[REG6:[0-9]+]], [[REG4]]
-; CHECK-DAG:   addze [[REG7:[0-9]+]], [[REG6]]
+; CHECK-DAG:   addze [[REG7:[0-9]+]], [[REG4]]
 ; CHECK-DAG:   addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc at ha
 ; CHECK-DAG:   andi. [[REG9:[0-9]+]], [[REG7]], 5
 ; CHECK-DAG:   stb [[REG9]], [[VAR2]]@toc at l([[REG8]])
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10222,7 +10222,9 @@
   // When the adde's carry is not used.
   if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
       N0.hasOneUse() && !N0.getNode()->hasAnyUseOfValue(1) &&
-      (!LegalOperations || TLI.isOperationLegal(N0.getOpcode(), VT))) {
+      // We only do for addcarry before legalize operation
+      ((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) ||
+       TLI.isOperationLegal(N0.getOpcode(), VT))) {
     SDLoc SL(N);
     auto X = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
     auto Y = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));


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