[llvm] r359030 - [AArch64][GlobalISel] Actually select G_INTRINSIC_TRUNC
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 13:46:19 PDT 2019
Author: paquette
Date: Tue Apr 23 13:46:19 2019
New Revision: 359030
URL: http://llvm.org/viewvc/llvm-project?rev=359030&view=rev
Log:
[AArch64][GlobalISel] Actually select G_INTRINSIC_TRUNC
Apparently FileCheck wasn't actually matching the fallback check lines in
arm64-vfloatintrinsics.ll properly. So, there were selection fallbacks for
G_INTRINSIC_TRUNC there.
Actually hook it up into AArch64InstructionSelector.cpp and write a proper
selection test.
I guess I'll figure out the FileCheck magic to make the fallback checks work
properly in arm64-vfloatintrinsics.ll.
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=359030&r1=359029&r2=359030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Tue Apr 23 13:46:19 2019
@@ -102,7 +102,7 @@ private:
bool selectIntrinsicWithSideEffects(MachineInstr &I,
MachineRegisterInfo &MRI) const;
bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
-
+ bool selectIntrinsicTrunc(MachineInstr &I, MachineRegisterInfo &MRI) const;
unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
MachineIRBuilder &MIRBuilder) const;
@@ -1847,6 +1847,8 @@ bool AArch64InstructionSelector::select(
return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
}
}
+ case TargetOpcode::G_INTRINSIC_TRUNC:
+ return selectIntrinsicTrunc(I, MRI);
case TargetOpcode::G_BUILD_VECTOR:
return selectBuildVector(I, MRI);
case TargetOpcode::G_MERGE_VALUES:
@@ -1866,6 +1868,61 @@ bool AArch64InstructionSelector::select(
return false;
}
+bool AArch64InstructionSelector::selectIntrinsicTrunc(
+ MachineInstr &I, MachineRegisterInfo &MRI) const {
+ const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
+
+ // Select the correct opcode.
+ unsigned Opc = 0;
+ if (!SrcTy.isVector()) {
+ switch (SrcTy.getSizeInBits()) {
+ default:
+ case 16:
+ Opc = AArch64::FRINTZHr;
+ break;
+ case 32:
+ Opc = AArch64::FRINTZSr;
+ break;
+ case 64:
+ Opc = AArch64::FRINTZDr;
+ break;
+ }
+ } else {
+ unsigned NumElts = SrcTy.getNumElements();
+ switch (SrcTy.getElementType().getSizeInBits()) {
+ default:
+ break;
+ case 16:
+ if (NumElts == 4)
+ Opc = AArch64::FRINTZv4f16;
+ else if (NumElts == 8)
+ Opc = AArch64::FRINTZv8f16;
+ break;
+ case 32:
+ if (NumElts == 2)
+ Opc = AArch64::FRINTZv2f32;
+ else if (NumElts == 4)
+ Opc = AArch64::FRINTZv4f32;
+ break;
+ case 64:
+ if (NumElts == 2)
+ Opc = AArch64::FRINTZv2f64;
+ break;
+ }
+ }
+
+ if (!Opc) {
+ // Didn't get an opcode above, bail.
+ LLVM_DEBUG(dbgs() << "Unsupported type for G_INTRINSIC_TRUNC!\n");
+ return false;
+ }
+
+ // Legalization would have set us up perfectly for this; we just need to
+ // set the opcode and move on.
+ I.setDesc(TII.get(Opc));
+ return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+}
+
bool AArch64InstructionSelector::selectVectorICmp(
MachineInstr &I, MachineRegisterInfo &MRI) const {
unsigned DstReg = I.getOperand(0).getReg();
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir?rev=359030&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir Tue Apr 23 13:46:19 2019
@@ -0,0 +1,198 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s
+
+...
+---
+name: test_f64.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_f64.intrinsic_trunc
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = FRINTZDr [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTZDr]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(s64) = COPY $d0
+ %1:fpr(s64) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_f32.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: test_f32.intrinsic_trunc
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = FRINTZSr [[COPY]]
+ ; CHECK: $s0 = COPY [[FRINTZSr]]
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:fpr(s32) = COPY $s0
+ %1:fpr(s32) = G_INTRINSIC_TRUNC %0
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_f16.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: test_f16.intrinsic_trunc
+ ; CHECK: liveins: $h0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
+ ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = FRINTZHr [[COPY]]
+ ; CHECK: $h0 = COPY [[FRINTZHr]]
+ ; CHECK: RET_ReallyLR implicit $h0
+ %0:fpr(s16) = COPY $h0
+ %1:fpr(s16) = G_INTRINSIC_TRUNC %0
+ $h0 = COPY %1(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: test_v4f16.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4f16.intrinsic_trunc
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = FRINTZv4f16 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTZv4f16_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s16>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v8f16.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8f16.intrinsic_trunc
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = FRINTZv8f16 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTZv8f16_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s16>) = COPY $q0
+ %1:fpr(<8 x s16>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f32.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v2f32.intrinsic_trunc
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = FRINTZv2f32 [[COPY]]
+ ; CHECK: $d0 = COPY [[FRINTZv2f32_]]
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s32>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v4f32.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v4f32.intrinsic_trunc
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = FRINTZv4f32 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTZv4f32_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:fpr(<4 x s32>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v2f64.intrinsic_trunc
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v2f64.intrinsic_trunc
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = FRINTZv2f64 [[COPY]]
+ ; CHECK: $q0 = COPY [[FRINTZv2f64_]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s64>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<2 x s64>)
+ RET_ReallyLR implicit $q0
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