[PATCH] D59780: Support Intel Control-flow Enforcement Technology

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm added a comment.

We are Ok with with the 2-PLT scheme.

>   I think I'd like **more opinions from others**.  **there are announcements but no design discussions**

Hi, Fangrui, the 2-PLT scheme has pass the ABI discussions, not H.J just made it by only himself.

>   **gives performance numbers demonstrating this second PLT scheme has indeed the cache-locality merit and is better than the alternative 24-byte PLT entry scheme**.

Yes, We really have not performance evidence, but this design is really more performance in theory, and this scheme has done years , and **nothing went wrong**.
The 24-bit plt is beautiful, but it is not the overwhelming reason to overthrow the big previous works.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D59780/new/

https://reviews.llvm.org/D59780