[PATCH] D60550: [X86] Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: include/llvm/IR/IntrinsicsX86.td:4833
+              [IntrNoMem]>;
+  // Intrinsic must be masked due to it producing less than 128 bits of results.
+  def int_x86_avx512bf16_mask_cvtneps2bf16_128:
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RKSimon wrote:
> Is there no way around this - other conversions don't need this.
I believe a lot of our masked conversion intrinsics never got their masking separated out to select in IR. So they haven't encountered this issue yet. I did put in MCVT* ISD opcodes for the older masked conversions to fix PR34877 a few months ago.

I do wonder if in a future state with strict FP support if we should keep the masking as part of all the floating point intrinsics.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D60550/new/

https://reviews.llvm.org/D60550