[PATCH] D60789: [x86] try to widen 'shl' as part of LEA formation

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1920-1921
+
+    // All of the bits that would have been shifted out must be 0 (nuw). That
+    // way, the wider shift can't preserve any 1 bits that should get killed.
+    APInt HighZeros = APInt::getHighBitsSet(Shl.getValueSizeInBits(),
----------------
This comment reads weird.
It is talking about the case like: https://rise4fun.com/Alive/DQd
Maybe something closer to
```
// The new shift must be NUW, that is, it must be safe to swap zext and shl around.
```


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1935
+    if (!matchAddressRecursively(NewShl, AM, Depth + 1))
+      return false;
+    break;
----------------
What about the `insertDAGNode()` calls? We simply expect that they will be dropped afterwards?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60789/new/

https://reviews.llvm.org/D60789