[PATCH] D60789: [x86] try to widen 'shl' as part of LEA formation

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, lebedev.ri, RKSimon.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

The test file has pairs of tests that are logically equivalent:
https://rise4fun.com/Alive/2zQ

  %t4 = and i8 %t1, 8
  %t5 = zext i8 %t4 to i16
  %sh = shl i16 %t5, 2
  %t6 = add i16 %sh, %t0
  =>
  %t4 = and i8 %t1, 8
  %sh2 = shl i8 %t4, 2
  %z5 = zext i8 %sh2 to i16
  %t6 = add i16 %z5, %t0

...so if we can fold the shift op into LEA in the 1st pattern, then we should be able to do the same in the 2nd pattern (unnecessary 'movzbl' is a separate bug I think).

We don't want to do this any sooner though because that would conflict with generic transforms that try to narrow the width of the shift.


https://reviews.llvm.org/D60789

Files:
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/test/CodeGen/X86/lea-dagdag.ll


Index: llvm/test/CodeGen/X86/lea-dagdag.ll
===================================================================
--- llvm/test/CodeGen/X86/lea-dagdag.ll
+++ llvm/test/CodeGen/X86/lea-dagdag.ll
@@ -21,10 +21,10 @@
 define i16 @and_i8_shl_zext_add_i16(i16 %t0, i8 %t1) {
 ; CHECK-LABEL: and_i8_shl_zext_add_i16:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    andb $8, %sil
-; CHECK-NEXT:    shlb $2, %sil
 ; CHECK-NEXT:    movzbl %sil, %eax
-; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    leal (%rdi,%rax,4), %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
@@ -52,10 +52,10 @@
 define i32 @and_i8_shl_zext_add_i32(i32 %t0, i8 %t1) {
 ; CHECK-LABEL: and_i8_shl_zext_add_i32:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    andb $8, %sil
-; CHECK-NEXT:    shlb $2, %sil
 ; CHECK-NEXT:    movzbl %sil, %eax
-; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    leal (%rdi,%rax,4), %eax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
   %sh = shl i8 %t4, 2
@@ -112,9 +112,8 @@
 ; CHECK-LABEL: and_i8_shl_zext_add_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $8, %sil
-; CHECK-NEXT:    shlb $2, %sil
 ; CHECK-NEXT:    movzbl %sil, %eax
-; CHECK-NEXT:    addq %rdi, %rax
+; CHECK-NEXT:    leaq (%rdi,%rax,4), %rax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
   %sh = shl i8 %t4, 2
@@ -142,8 +141,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    andl $8, %esi
-; CHECK-NEXT:    leal (,%rsi,4), %eax
-; CHECK-NEXT:    addq %rdi, %rax
+; CHECK-NEXT:    leaq (%rdi,%rsi,4), %rax
 ; CHECK-NEXT:    retq
   %t4 = and i32 %t1, 8
   %sh = shl i32 %t4, 2
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1906,6 +1906,35 @@
 
     break;
   }
+  case ISD::ZERO_EXTEND: {
+    // Try to widen a zexted shift left to the same size as its use, so we can
+    // match the shift as a scale factor.
+    if (N.getOperand(0).getOpcode() != ISD::SHL || !N.getOperand(0).hasOneUse())
+      break;
+
+    SDValue Shl = N.getOperand(0);
+    auto *ShAmtC = dyn_cast<ConstantSDNode>(Shl.getOperand(1));
+    if (!ShAmtC)
+      break;
+
+    // All of the bits that would have been shifted out must be 0 (nuw). That
+    // way, the wider shift can't preserve any 1 bits that should get killed.
+    APInt HighZeros = APInt::getHighBitsSet(Shl.getValueSizeInBits(),
+                                            ShAmtC->getZExtValue());
+    if (!CurDAG->MaskedValueIsZero(Shl.getOperand(0), HighZeros))
+      break;
+
+    // zext (shl X, C) --> shl (zext X), C
+    MVT VT = N.getSimpleValueType();
+    SDLoc DL(N);
+    SDValue Zext = CurDAG->getNode(ISD::ZERO_EXTEND, DL, VT, Shl.getOperand(0));
+    insertDAGNode(*CurDAG, Shl.getOperand(0), Zext);
+    SDValue NewShl = CurDAG->getNode(ISD::SHL, DL, VT, Zext, Shl.getOperand(1));
+    insertDAGNode(*CurDAG, N, NewShl);
+    if (!matchAddressRecursively(NewShl, AM, Depth + 1))
+      return false;
+    break;
+  }
   }
 
   return matchAddressBase(N, AM);


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