[PATCH] D60708: [ARM] Code-generation infrastructure for MVE.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added a comment.

Can any of this be tested yet, or are we still missing some patches?



================
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:809
+void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
+{
+  MIB.addImm(ARMVCC::None);
----------------
Style nit: opening brace should be on the line above.


================
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:933
     return;
+  } else if (DestReg == ARM::VPR) {
+    BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
----------------
Should we assert that the other register is a GPR here?


================
Comment at: llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp:206
     unsigned PredReg = 0;
-    ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
-    if (CC == ARMCC::AL) {
-      ++MBBI;
-      continue;
-    }
+    ARMCC::CondCodes CC;
+
----------------
Does anything generate VPT-predicated instructions yet? If not, this should probably be split into a separate patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D60708/new/

https://reviews.llvm.org/D60708