[PATCH] D60358: [TargetLowering][X86][AArch64] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I think D60482 <https://reviews.llvm.org/D60482> should go in 1st, so we avoid that known regression. There's still an open question about the x86 LEA matching. I've seen that or similar matching failures in other tests, so it would be nice to catch it first too.

I wonder if losing the wrapping flags is hurting. Although we should be able to use knownbits to restore the knowledge. Something like this?

  define i64 @lea(i64 %t0, i32 %t1) {
    %t4 = add nuw nsw i32 %t1, 8
    %sh = shl nsw i32 %t4, 2
    %t5 = zext i32 %sh to i64
    %t6 = add i64 %t5, %t0
    ret i64 %t6
  }

Produces:
	leal	32(,%rsi,4), %eax
	addq	%rdi, %rax

Instead of:
	leaq	32(%rdi,%rsi,4), %rax


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60358/new/

https://reviews.llvm.org/D60358