[PATCH] D60394: [X86] Add patterns for using movss/movsd for atomic load/store of f32/64. Remove atomic fadd pseudos use isel patterns instead.

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked an inline comment as done.
craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/X86/atomic-fp.ll:147
 ; X86-AVX-NEXT:    lock cmpxchg8b (%esi)
 ; X86-AVX-NEXT:    jne .LBB1_1
 ; X86-AVX-NEXT:  # %bb.2: # %atomicrmw.end
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RKSimon wrote:
> Can we improve the i686 i64/f64 codegen at all?
Yeah we need to add something like a v2i64 VEXTRACT_STORE node and turn the atomic store into that then select that to the MOVQ store. Maybe some more work depending on how the (v2i64 (scalar_to_vector (i64 (bitcast f64)))) that implies gets legalized and cleaned up

This only work if the atomic store isn't seq_cst. seq_cst either requires the locked cmpxchg8b that we have now or we need an mfence after the movq. gcc and icc both use the movq+mfence(or a locked or to stack if mfence isn't available) I think.


Repository:
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  https://reviews.llvm.org/D60394/new/

https://reviews.llvm.org/D60394