[PATCH] D60394: [X86] Add patterns for using movss/movsd for atomic load/store of f32/64. Remove atomic fadd pseudos use isel patterns instead.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/X86/atomic-fp.ll:8
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -verify-machineinstrs | FileCheck %s --check-prefix X64 --check-prefix X64-AVX --check-prefix X64-AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -verify-machineinstrs | FileCheck %s --check-prefix X64 --check-prefix X64-AVX --check-prefix X64-AVX512
 
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Maybe add SSE1 only tests?


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Comment at: llvm/test/CodeGen/X86/atomic-fp.ll:147
 ; X86-AVX-NEXT:    lock cmpxchg8b (%esi)
 ; X86-AVX-NEXT:    jne .LBB1_1
 ; X86-AVX-NEXT:  # %bb.2: # %atomicrmw.end
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Can we improve the i686 i64/f64 codegen at all?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D60394/new/

https://reviews.llvm.org/D60394