[PATCH] D60358: [TargetLowering][X86][AArch64] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11041-11045
+  // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
+  if (Op->getOpcode() == ISD::ANY_EXTEND &&
+      Bit < Op->getOperand(0).getValueSizeInBits()) {
+    return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
+  }
----------------
It would be better to split this change off on its own while adding a test specifically for this pattern.

IIUC, we can modify the existing test slightly and show the missing fold:


```
declare void @t()
define void @tbz_zext(i32 %in) {
  %shl = shl i32 %in, 3
  %t = zext i32 %shl to i64
  %and = and i64 %t, 32
  %cond = icmp eq i64 %and, 0
  br i1 %cond, label %then, label %end

then:
  call void @t()
  br label %end

end:
  ret void
}

```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60358/new/

https://reviews.llvm.org/D60358