[PATCH] D60333: [X86][SSE] SimplifyDemandedBitsForTargetNode - Add PACKSS support

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

In D60333#1456942 <https://reviews.llvm.org/D60333#1456942>, @RKSimon wrote:

> I agree, I hope to do that in the future (and something similar for PACKUS) once I have suitable test coverage (its related to better support for TRUNCATE vector SimplifiedDemandedBits support as well) - but for now I'd prefer just to get this MOVMSK fix in.


Sounds good. The sign bit case is rather different from the rest.



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:33513
+  case X86ISD::PACKSS:
+    // PACKSS saturates to -ve/+ve max integer value. So if we just want the
+    // sign bit then we can just ask for the source operands sign bit.
----------------
What does `-ve/+ve` mean?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:33526
+                               KnownRHS, TLO, Depth + 1))
+        return true;
+    }
----------------
Could use the known bits to determine the sign bit:

```
if (KnownLHS.isNegative() && KnownRHS.isNegative())
  Known.makeNegative();
else if (KnownLHS.isNonNegative() && KnownRHS.isNonNegative())
  Known.makeNonNegative();
```


Repository:
  rL LLVM

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  https://reviews.llvm.org/D60333/new/

https://reviews.llvm.org/D60333