[PATCH] D60212: [AArch64] Add lowering pattern for scalar fp16 facge and facgt

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio updated this revision to Diff 193674.
dnsampaio added a comment.

Attended requests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60212/new/

https://reviews.llvm.org/D60212

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll


Index: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
===================================================================
--- test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
+++ test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
@@ -7,6 +7,8 @@
 declare half @llvm.aarch64.neon.frecps.f16(half, half)
 declare half @llvm.aarch64.neon.fmulx.f16(half, half)
 declare half @llvm.fabs.f16(half)
+declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half)
+declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half)
 
 define dso_local half @t_vabdh_f16(half %a, half %b) {
 ; CHECK-LABEL: t_vabdh_f16:
@@ -318,3 +320,25 @@
   %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
   ret i32 %vcvth_n_u32_f16
 }
+
+define dso_local i16 @vcageh_f16_test(half %a, half %b) {
+; CHECK-LABEL: vcageh_f16_test:
+; CHECK:        facge   h0, h0, h1
+; CHECK-NEXT:   fmov    w0, s0
+; CHECK-NEXT:   ret
+entry:
+  %facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b)
+  %0 = trunc i32 %facg to i16
+  ret i16 %0
+}
+
+define dso_local i16 @vcagth_f16_test(half %a, half %b) {
+; CHECK-LABEL: vcagth_f16_test:
+; CHECK:        facgt   h0, h0, h1
+; CHECK-NEXT:   fmov    w0, s0
+; CHECK-NEXT:   ret
+entry:
+  %facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)
+  %0 = trunc i32 %facg to i16
+  ret i16 %0
+}
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -5355,6 +5355,16 @@
             (i64 (IMPLICIT_DEF)),
             (FCVTZUh FPR16:$Rn, vecshiftR64:$imm),
             hsub))>;
+def : Pat<(i32 (int_aarch64_neon_facge (f16 FPR16:$Rn), (f16 FPR16:$Rm))),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FACGE16 FPR16:$Rn, FPR16:$Rm),
+            hsub))>;
+def : Pat<(i32 (int_aarch64_neon_facgt (f16 FPR16:$Rn), (f16 FPR16:$Rm))),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FACGT16 FPR16:$Rn, FPR16:$Rm),
+            hsub))>;
 
 defm SHL      : SIMDScalarLShiftD<   0, 0b01010, "shl", AArch64vshl>;
 defm SLI      : SIMDScalarLShiftDTied<1, 0b01010, "sli">;


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