[PATCH] D60212: [AArch64] Add lowering pattern for scalar fp16 facge and facgt

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:322
+
+declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half)
+define dso_local i16 @vcageh_f16_test(half %a, half %b) {
----------------
move the declares to the top like the rest of the tests.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:326
+; CHECK:        facge   h0, h0, h1
+; CHECK-NEXT:        fmov    w0, s0
+; CHECK-NEXT:        ret
----------------
fix/alignindentation


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60212/new/

https://reviews.llvm.org/D60212