[PATCH] D58736: [System Model] Introduce a target system model

[David Greene via Phabricator via llvm-commits]

greened added a comment.

In D58736#1434370 <https://reviews.llvm.org/D58736#1434370>, @simoll wrote:

> This takes a while to digest. Some quick remarks for now (also inline):


Yes, I know it's a big patch.  I wanted to provide the whole context but can certainly break it up into smaller pieces for review if that's easier.  Would it be useful to post smaller pieces for review/commit but maintain this patch for reference?  I don't intend to actually commit all this as one big change.

> - Is there a way to query the number of (automatic) HW prefetchers?

Not currently.  It's something we could add later.

> - Does the interface provide the latency of each cache level (hit)/memory (miss)?

The latency of each level is the latency for a hit.  I hadn't considered a separate miss latency as I thought the last "level" would be DRAM and the latency for that would approximate the latency of a full miss.  Of course the various cache levels will have a longer miss latency than a direct DRAM access but I hadn't considered that overhead to be arge enough to model.  If we think it is then we can do that.


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https://reviews.llvm.org/D58736