[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

Tue Apr 2 09:06:58 PDT 2019

RKSimon added a comment.

In D59758#1451337 <https://reviews.llvm.org/D59758#1451337>, @spatel wrote:

> Thanks for expanding on the x86 example. I agree now that it's a good idea to try these optimizations.
>  @RKSimon may know from looking, but this might mean we can remove the more specific fold from rL357351 <https://reviews.llvm.org/rL357351> ?

IIRC that transform was being done pre-DAG - so the OR was already stuck on the wrong side of the zext - would be interested to see though (we still don't match PAVGB if it uses OR after ZEXT).

Something I didn't do but I think would be useful is to add a 'bool SelectionDAG::isAddLike(SDValue N, SDValue &Op0, SDValue &Op1)' helper that will match against ADD/OR/SHL etc. that all perform some form of addition.

================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2230
+      return V;
+  }

----------------
I realise it reduces the patch - but would it be better to move this in the new visitAdd?

================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2236
   // fold (a+b) -> (a|b) iff a and b share no bits.
-  if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
+  if (IsAdd && (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
       DAG.haveNoCommonBitsSet(N0, N1))
----------------
move this in the new visitAdd?

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https://reviews.llvm.org/D59758